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| ds07-13504-2e fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos f 2 mc-16f mb90230 series mb90233/234/p234/w234 n description the mb90230 series is a member of general-purpose, 16-bit microcontrollers designed for those applications which require high-speed realtimeprocessing, proving to be suitable for various industrial machines, camera and video devices, oa equipment, and for process control. the cpu used in this series is the f 2 mc*-16f. the instruction set for the f 2 mc-16f cpu core is designed to be optimized for controller applications while inheriting the at architecture of the f 2 mc-16/16h series, allowing a wide range of control tasks to be processed efficiently at high speed. the peripheral resources integrated in the mb90230 series include: the uart (clock asynchronous/synchronous transfer) 1 channel, the extended serial i/o interface 1 channel, the a/d converter (8/10-bit precision) 8 channels, the d/a converter (8-bit precision) 2 channels, the level comparator 1 channel, the external interrupt input 4 lines, the 8-bit ppg timer (pwm/single-shot function) 1 channel, the 8-bit pwm controller 6 channels, the 16-bit free run timer 1 channel, the input capture unit 4 channels, the output compare unit 6 channels, and the serial e 2 prom interface. *: f 2 mc stands for fujitsu flexible microcontroller. n features f 2 mc-16f cpu block ? minimum execution time: 62.5 ns (at machine clock frequency of 16 mhz) ? instruction set optimized for controllers various data types supported (bit, byte, word, and long-word) extended addressing modes: 23 types high coding efficiency higher-precision operation enhanced by a 32-bit accumulator signed multiplication and division instructions (continued) n package 100-pin plastic lqfp (fpt-100p-m05) 100-pin ceramic lqfp (fpt-100c-c01)
mb90230 series 2 (continued) ? enhanced instructions applicable to high-level language (c) and multitasking system stack pointer enhanced pointer-indirect instructions barrel shift instructions ? increased execution speed: 8-byte instruction queue ? 8-level, 32-factor powerful interrupt service functions ? automatic transfer function independent of the cpu (ei 2 os) ? general-purpose ports: up to 84 lines ports with input pull-up resistor available: 24 lines ports with output open-drain available: 9 lines peripheral blocks ? rom:48 kbytes (mb90233) 96 kbytes (mb90234) eprom: 96 kbytes (MB90W234) one-time prom: 96 kbytes (mb90p234) ? ram: 2 kbytes (mb90233) 3 kbytes (mb90234/w234/p234) ? pwm control circuit: (simple 8 bits): 6 channels ? serial interface uart: 1 channel extended serial i/o interface switchable i/o port: 1 channel communication prescaler (source clock generator for the uart, serial i/o interface, ckot, and level comparator): 1 channel ? serial e 2 prom interface: 1 channel ? a/d converter with 8/10-bit resolution: input 8 channels ? level comparator: 1 channel 4-bit d/a converter integrated ? d/a converter with 8-bit resolution: 2 channels 8-bit ppg timer: 1 channel ? input/output timer 16-bit free run timer: 1 channel 16-bit output compare unit: 6 channels 16-bit input capture unit: 4 channels ? 18-bit timebase timer ? watchdog timer function ? standby modes sleep mode stop mode 3 mb90230 series n product lineup nb90234 mb90p234 MB90W234 mb90v230 classification mask rom products one-time prom model eprom model evaluation model rom size 48 kbytes 96 kbytes 96 kbytes 96 kbytes ram size 2 kbytes 3 kbytes 3 kbytes 3 kbytes 4 kbytes cpu functions number of instructions: 420 instruction bit length: 8 or 16 bits instruction length: 1 to 7 bytes data bit length: 1, 4, 8, 16, or 32 bits minimum execution time: 62.5 ns at 16 mhz (internal) ports up to 84 lines i/o ports (cmos): 51 i/o ports (cmos) with pull-up resistor available: 24 i/o ports (open-drain): 9 uart number of channels: 1 (switchable i/o) clock synchronous communication (2404 to 38460 bps, full-duplex double buffering) clock asynchronous communication (500k to 5m bps, full-duplex double buffering) serial interface number of channels: 1 internal or external clock mode clock synchronous transfer (62.5 khz to 1 mhz, lsb first or msb first transfer) a/d converter resolution: 10 or 8 bits, number of input lines: 4 single conversion mode (conversion for a specified input channel) scan conversion mode (continuous conversion for specified consecutive channels) continuous conversion mode (repeated conversion for a specified channel) stop conversion mode (periodical conversion) d/a converter resolution: 8 bits, number of output pins: 2 level comparator comparison to internal d/a converter (4-bit resolution) pwm number of channels: 6 8-bit pwm control circuit (operation of 1 f , 2 f , 16 f , 32 f ) ppg timer number of channels: 1 channel with 8-bit resolution pwm function: continuous output of pulse synchronous to trigger single-shot function: output of single pulse by trigger serial e 2 prom interface number of channels: 1 instruction code (ns type) variable address length: 8 to 11 bits (with address increment function) variable data length: 8 or 16 bits timer number of channels: 6 16-bit reload timer operation (operation clock cycle of 0.25 m s to 1.05 s) free run timer number of channels: 1 16-bit input capture unit: 4 channels 16-bit output compare unit: 6 channels external interrupt input number of input pins: 4 standby mode stop mode and sleep mode package fpt-100p-m05 fpt-100c-c01 pga256-a02 mb90233 parameter part number mb90230 series 4 n pin assignment 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 rst p54/wrh p53/hrq p52/hak p51/rdy p50/clk pa5/sck2 pa4/sot2 pa3/sin2 pa2/sck1 pa1/sot1 pa0/sin1 p96/sck0 p95/sot0 p94/sin0 p93/in3/ckot p92/in2 p91/in1 p90/in0 p87/out5 p86/out4 p85/out3 p84/out2 p83/out1/int3 p82/out0/int2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 p22/a02 p23/a03 p24/a04 p25/a05 p26/a06 p27/a07 p30/a08 p31/a09 v ss p32/a10 p33/a11 p34/a12 p35/a13 p36/a14 p37/a15 pwm0/p40/a16 pwm1/p41/a17 pwm2/p42/a18 pwm3/p43/a19 pwm4/p44/a20 v cc pwm5/p45/a21 trg/p46/a22 ppg/p47/a23 atg/p70 p71/edi p72/edo p73/esk p74/ecs p75/da0 p76/da1 av cc avrh avrl av ss p60/an0 p61/an1 p62/an2 p63/an3 v ss p64/an4 p65/an5 p66/an6 p67/an7/cmp p80/int0 p81/int1 md0 md1 md2 hst p21/a01 p20/a00 p17/d15 p16/d14 p15/d13 p14/d12 p13/d11 p12/d10 p11/d09 p10/d08 p07/d07 p06/d06 p05/d05 p04/d04 p03/d03 p02/d02 p01/d01 p00/d00 v cc x1 x0 v ss p57 p56/rd p55/wrl (top view) 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 (fpt-100p-m05) (fpt-100c-c01) 5 mb90230 series n pin description (continued) pin no. pin name circuit type function 80 x0 a oscillator pins 81 x1 82 v cc power supply pin 83 to 90 p00 to p07 g general-purpose i/o port an input pull-up resistor can be added to the port by setting the pull-up resistor setting register. these pins serve as d00 to d07 pins in bus modes other than the single-chip mode. d00 to d07 i/o pins for the lower eight bits of the external data bus. these pins are enabled in an external-bus enabled mode. 91 to 98 p10 to p17 g general-purpose i/o port an input pull-up resistor can be added to the port by setting the pull-up resistor setting register. these pins are enabled in the single-chip mode with the external-bus enabled and the 8-bit data bus specified. d08 to d15 i/o pins for the upper eight bits of the external data bus these pins are enabled in an external-bus enabled mode with the 16- bit data bus specified. 99, 100 1 to 6 p20 to p27 g general-purpose i/o port an input pull-up resistor can be added to the port by setting the pull-up resistor setting register. these pins are enabled in the single-chip mode. a00 to a07 i/o pins for the lower eight bits of the external data bus these pins are enabled in an external-bus enabled mode. 7, 8 p30, p31 e general-purpose i/o port this port is enabled in the single-chip mode or when the middle address control register setting is port. a08, a09 i/o pins for the middle eight bits of the external data bus these pins are enabled in an external-bus enabled mode when the middle address control register setting is address. 9v ss power supply pin 10 to 15 p32 to p37 e general-purpose i/o port this port is enabled in the single-chip mode or when the middle address control register setting is port. a10 to a15 i/o pins for the middle eight bits of the external data bus these pins are enabled in an external-bus enabled mode when the middle address control register setting is address. mb90230 series 6 (continued) pin no. pin name circuit type function 16 p40 e general-purpose i/o port this port is enabled in the single-chip mode or when the upper address control register setting is port. a16 output pin for external address a16 this pin is enabled in the external-bus enabled mode with the upper address control register set to address. pwm0 this pin serves as the output pin for 8-bit pwm0 the pin is enabled for output by the control status register. 17 p41 e general-purpose i/o port this port is enabled in the single-chip mode or when the upper address control register setting is port. a17 output pin for external address a17 this pin is enabled in the external-bus enabled mode with the upper address control register set to address. pwm1 this pin serves as the output pin for 8-bit pwm1. the pin is enabled for output by the control status register. 18 p42 e general-purpose i/o port this port is enabled in the single-chip mode or when the upper address control register setting is port. a18 output pin for external address a18 this pin is enabled in the external-bus enabled mode with the upper address control register set to address. pwm2 this pin serves as the output pin for 8-bit pwm2. this pin is enabled for output by the control status register. 19 p43 e general-purpose i/o port this port is enabled in the single-chip mode or when the upper address control register setting is port. a19 output pin for external address a19 this pin is enabled in the external-bus enabled mode with the upper address control register set to address. pwm3 this pin serves as the output pin for 8-bit pwm3. this pin is enabled for output by the control status register. 20 p44 e general-purpose i/o port this port is enabled in the single-chip mode or when the upper address control register setting is port. a20 output pin for external address a20 this pin is enabled in the external-bus enabled mode with the upper address control register set to address. pwm4 this pin serves as the output pin for 8-bit pwm4. the pin is enabled for output by the control status register. 21 v cc power supply pin 7 mb90230 series (continued) pin no. pin name circuit type function 22 p45 e general-purpose i/o port this port is enabled in the single-chip mode or when the upper address control register setting is port. a21 output pin for external address a21 this pin is enabled in the external-bus enabled mode with the upper address control register set to address. pwm5 this pin serves as the output pin for 8-bit pwm5. the pin is enabled for output by the control status register. 23 p46 l* 1 general-purpose i/o port this port is enabled in the single-chip mode or when the upper address control register setting is port. a22 output pin for external address a22 this pin is enabled in the external-bus enabled mode with the upper address control register set to address. trg this pin serves as the external trigger pin for the 8-bit ppg timer the pin is enabled for triggering by the control status register. 24 p47 e general-purpose i/o port this port is enabled in the single-chip mode or when the upper address control register setting is port. a23 output pin for external address a23 this pin is enabled in the external-bus enabled mode with the upper address control register set to address. ppg this pin serves as the output pin for the 8-bit ppg timer. the pin is enabled for output by the control status register. 25 p70 l* 1 general-purpose i/o port at g external trigger input pin for the a/d converter this pin functions when enabled by the control status register. 26 p71 f general-purpose i/o port edi data input pin for the serial eeprom interface this pin functions when enabled by the control status register. 27 p72 e general-purpose i/o port edo data output pin for the serial eeprom interface this pin functions when enabled by the control status register. 28 p73 e general-purpose i/o port esk clock output pin for the serial eeprom interface this pin functions when enabled by the control status register. 29 p74 e general-purpose i/o port ecs chip select signal output pin for the serial eeprom interface this pin functions when enabled by the control status register. mb90230 series 8 (continued) pin no. pin name circuit type function 30, 31 p75, p76 k general-purpose i/o port da0 da1 this pin serves as the d/a converter output pin. the pin functions when enabled by the control status register. 32 av cc a/d converter power supply pin 33 av rh h reference power supply pin for the a/d converter 34 av rl l reference power supply pin for the a/d converter 35 av ss a/d converter power pin (gnd) 36 to 39 p60 to p63 j general-purpose i/o port this port is enabled when the analog input enable register setting is port. an0 to an3 a/d converter analog input pins these pins are enabled when the analog input enable register setting is analog input. 40 v ss power pin (gnd) 41 to 43 p64 to p66 j general-purpose i/o port this port is enabled when the analog input enable register setting is port. an4 to an6 a/d converter analog input pins these pins are enabled when the analog input enable register setting is analog input. 44 p67 j general-purpose i/o port this port is enabled when the analog input enable register setting is port. an7 a/d converter analog input pin this pin is enabled when the analog input enable register setting is analog input. cmp comparator input pin 45 p80 l* 2 general-purpose i/o port this port is always enabled. int0 external interrupt request input 0 since this pin serves for interrupt request as required when external interrupt is enabled, other outputs must be off unless used intentionally. 46 p81 l* 2 general-purpose i/o port this port is always enabled. int1 external interrupt request input 1 since this pin serves for interrupt request as required when external interrupt is enabled, other outputs must be off unless used intentionally. 47 md0 c mode pin this pin must be fixed to v cc or v ss . 48 md1 c mode pin this pin must be fixed to v cc or v ss . 9 mb90230 series (continued) pin no. pin name circuit type function 49 md2 c mode pin this pin must be fixed to v ss . 50 hst d hardware standby input pin 51, 52 p82, p83 l* 2 general-purpose i/o port out0, out1 output compare output pins these pins function when enabled by the control status register. int2, int3 external interrupt request inputs 2 and 3. since these pins serve for interrupt request as required when external interrupt is enabled, other outputs must be off unless used intentionally. 53 to 56 p84 to p87 e general-purpose i/o port this pin is always enabled. out2 to out5 output compare output pins these pins function when enabled by the control status register. 57 to 59 p90 to p92 l* 1 general-purpose i/o port this port is always enabled. in0 to in2 input capture edge input pins these pins function when enabled by the control status register. 60 p93 l* 1 general-purpose i/o port this port is always enabled. in3 input capture edge input pin this pin functions when enabled by the control status register. ckot prescaler output pin this pin functions when enabled by the control status register. 61 p94 i general-purpose i/o port this port is always enabled. the port serves as an open-drain output depending on the open-drain setting register. sin0 serial data input pin for the uart this pin functions when enabled by the control status register. 62 p95 h general-purpose i/o port this port is always enabled. the port serves as an open-drain output depending on the open-drain setting register. sot0 serial data output pin for the uart this pin functions when enabled by the control status register. 63 p96 i general-purpose i/o port this port is always enabled. the port serves as an open-drain output depending on the open-drain setting register. sck0 uart clock output pin this pin functions when enabled by the control status register. mb90230 series 10 (continued) pin no. pin name circuit type function 64 pa0 i general-purpose i/o port this port is always enabled. the port serves as an open-drain output depending on the open-drain setting register. sin1 serial data input pin for the extended serial i/o interface this pin functions when enabled by the control status register and by the serial port switching register. 65 pa1 h general-purpose i/o port this port is always enabled. the port serves as an open-drain output depending on the open-drain setting register. sot1 serial data output pin for the extended serial i/o interface this pin functions when enabled by the control status register and by the serial port switching register. 66 pa2 i general-purpose i/o port this port is always enabled. the port serves as an open-drain output depending on the open-drain setting register. sck1 clock output pin for the extended serial i/o interface this pin functions when enabled by the control status register and by the serial port switching register. 67 pa3 i general-purpose i/o port this port is always enabled. the port serves as an open-drain output depending on the open-drain setting register. sin2 serial data input pin for the extended serial i/o interface this pin functions when enabled by the control status register and by the serial port switching register. 68 pa4 h general-purpose i/o port this port is always enabled. the port serves as an open-drain output depending on the open-drain setting register. sot2 serial data output pin for the extended serial i/o interface this pin functions when enabled by the control status register and by the serial port switching register. 69 pa5 i general-purpose i/o port this port is always enabled. the port serves as an open-drain output depending on the open-drain setting register. sck2 clock output pin for the extended serial i/o interface this pin functions when enabled by the control status register and by the serial port switching register. the pin is a general-purpose i/o port. 11 mb90230 series (continued) *1: enabled in any standby mode *2: enabled only in the hardware standby mode pin no. pin name circuit type function 70 p50 h this pin is enabled in the single-chip mode and when the clk output is disabled. clk clk output pin this pin is enabled in an external-bus enabled mode with the clk output enabled. 71 p51 f general-purpose i/o port this port is enabled in the single-chip mode. rdy ready signal input pin this pin is enabled in an external-bus enabled mode. 72 p52 e general-purpose i/o port this port is enabled in the single-chip mode or when the hold function is disabled. hak hold acknowledge signal output pin this pin is enabled in the single-chip mode or when the hold function is enabled. 73 p53 e general-purpose i/o port this port is enabled in the single-chip mode or when the hold function is disabled. hrq hold acknowledge signal output pin this pin is enabled in the single-chip mode or when the hold function is enabled. 74 p54 e general-purpose i/o port this port is enabled in the single-chip mode, in external-bus 8-bit mode, or when the wr pin output is disabled. wrh write strobe output pin for the upper eight bits of the data bus this pin is enabled in an external-bus enabled mode and in external bus 16-bit mode with the wr pin output enabled. 75 rst b reset signal input pin 76 p55 e this port is enabled in the single-chip mode, in external-bus 8-bit mode, or when the wr pin output is disabled wrl write strobe output pin for the lower eight bits of the data bus this pin is enabled in an external-bus enabled mode and in external bus 16-bit mode with the wr pin output enabled. the pin is a general-purpose i/o port. 77 p56 e this pin is enabled in the single-chip mode. rd read strobe output pin for the data bus this pin is enabled in an external-bus enabled mode. 78 p57 e general-purpose i/o port 79 v ss power pin (gnd) mb90230 series 12 n i/o circuit type (continued) type circuit remarks a ? oscillation feedback resistor: approx. 1 m w b ? hysteresis input with pull-up resistor c?cmos input port d ? hysteresis input port e ? cmos level output x1 x0 standby control standby control cmos 13 mb90230 series (continued) type circuit remarks f ? cmos level output ? hysteresis input g ? input pull-up resistor control provided ? cmos level input/output h ? cmos level input/output ? open-drain control provided standby control standby control cmos pull-up control cmos open-drain control signal standby control mb90230 series 14 (continued) type circuit remarks i ? cmos level output ? hysteresis input ? open-drain control provided j ? cmos level input/output ? analog input k ? cmos level input/output ? analog output ? also serving for d/a output l ? cmos level output ? hysteresis input ? open-drain control provided cmos open-drain control signal standby control cmos analog input standby control cmos da output standby control standby control open-drain control signal 15 mb90230 series n handling devices 1. preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- to high-voltage pins or if higher than the voltage wihich shows on 1. absolute maximum ratings in section n electrical characteristics is applied between v cc and v ss . when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. also, take care to prevent the analog power supply (av cc and avr) and analog input from exceeding the digital power supply (v cc ) when the analog system power supply is turned on and off. 2. treatment of unused pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistor. 3. external reset input to reset the internal circuit by the low-level input to the rst pin, the low-level input to the rst pin must be maintained for at least five machine cycles. pay attention to it if the chip uses external clock input. 4. v cc and v ss pins apply equal potential to the v cc and v ss pins. 5. notes on using an external clock when using an external clock, drive the x0 pin as illustrated below: 6. power-on sequence for a/d converter power supplies and analog inputs be sure to turn on the digital power supply (v cc ) before applying voltage to the a/d converter power supplies (av cc , avrh, and avrl) and analog inputs (an0 to an15). when turning power supplies off, turn off the a/d converter power supplies (av cc , avrh, and avrl) and analog inputs (an0 to an15) first, then the digital power supply (av cc ). when turning avrh on or off, be careful not to let it exceed av cc . 7. pin set when turning on power supplies when turning on power supplies, set the hardware standby input pin (hst ) to h. use of external clock x0 x1 mb90234 mb90230 series 16 8. program mode when shipped from fujitsu, and after each erasure, all bits (96k 8 bits) in the MB90W234 and mb90p234 are in the 1 state. data is introduced by selectively programming 0s into the desired bit locations. bits cannot be set to 1 electrically. 9. erasure procedure data written in the MB90W234 is erased (from 0 to 1) by exposing the chip to ultraviolet rays with a wavelength of 2,537? through the translucent cover. recommended irradiation dosage for exposure is 10 wsec/cm 2 . this amount is reached in 15 to 20 minutes with a commercial ultraviolet lamp positioned 2 to 3 cm above the package (when the package surface illuminance is 1200 m w/cm 2 ). if the ultraviolet lamp has a filter, remove the filter before exposure. attaching a mirrored plate to the lamp increases the illuminance by a factor of 1.4 to 1.8, thus shortening the required erasure time. if the translucent part of the package is stained with oil or adhesive, transmission of ultraviolet rays is degraded, resulting in a longer erasure time. in that case, clean the translucent part using alcohol (or other solvent not affecting the package). the above recommended dosage is a value which takes the guard band into consideration and is a multiple of the time in which all bits can be evaluated to have been erased. observe the recommended dosage for erasure; the purpose of the guard band is to ensure erasure in all temperature and supply voltage ranges. in addition, check the lifespan of the lamp and control the illuminance appropriately. data in the MB90W234 is erased by exposure to light with a wavelength of 4000? or less. data in the device is also erased even by exposure to fluorescent lamp light or sunlight although the exposure results in a much lower erasure rate than exposure to 2537? ultraviolet rays. note that exposure to such lights for an extended period will therefore affect system reliability. if the chip is used where it is exposed to any light with a wavelength of 4000? or less, cover the translucent part, for example, with a protective seal to prevent the chip from being exposed to the light. exposure to light with a wavelength of 4,000 to 5,000? or more will not erase data in the device. if the light applied to the chip has a very high illuminance, however, the device may cause malfunction in the circuit for reasons of general semiconductor characteristics. although the circuit will recover normal operation when exposure is stopped, the device requires proper countermeasures for use in a place exposed continuously to such light even though the wavelength is 4,000? or more. 17 mb90230 series 10. recommended screening conditions high-temperature aging is recommended for screening before packaging. 11. write yield otprom products cannot be write-tested for all bits due to their nature. therefore the write yield cannot always be guaranteed to be 100%. program, verify aging +150?, 48 hrs. data verification assembly mb90230 series 18 n block diagram ram interrupt controller f 2 mc-16 bus 8 8 8 8 8 8 8 78 p00 to p07 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p70 to p76 p80 to p87 i/o ports (84 lines) cpu f 2 mc-16f rom 8-bit ppg timer i/o timer in0, 1 in2, 3 level comparator 7 p90 to p96 cmp 6 pa0 to pa5 4 x0, x1 rst hst trg ppg external interrupt uart sin0 sot0 sck0 ckot extended serial i/o interface sin1, 2 sot1, 2 sck1, 2 10-bit a/d converter avcc avrh, avrl avss atg an0 to an7 d/a converter 16-bit input capture 4 16-bit output compare 6 16-bit free run timer da0 da1 p00 to p27 (24 lines): provided with input pull-up resistor setting registers p94 to p96, pa0 to pa5 (9 lines): provided with open-drain setting registers int0 to int3 communication prescaler 4 8-bit pwm pwm0 to pwm5 6 ch out0, 1 out2, 3 out4, 5 serial e 2 prom interface 2 ecs, esk edo edi clock controller 19 mb90230 series n memory map the mb90230 series can access the 00 bank to read rom data written to the upper 48-kb locations in the ff bank. an advantage of reading written to data addresses ffffff h -ff4000 h from addresses 00ffff h -004000 h is that you can use the small model of a c compiler. note, however, that the products with more than 48kb rom space (mb90v230, mb90p/w234, mb90234) cannot read data in addresses other than ffffff h to ff4000 h from the 00 bank. ffffff h address1# 00ffff h address#2 address#3 000100 h 0000c0 h 000000 h single-chip mode internal rom and external bus external rom and external bus rom area rom area rom area (ff bank image) rom area (ff bank image) ram registers ram registers ram registers peripherals peripherals peripherals internal external inhibited area 000000 h to 000005 h and 000010 h to 000015 h are allocated for external use when the external bus is enabled. note: address#3 address#2 address#1 product type mb90233 mb90v230 mb90234 mb90p234 MB90W234 ff4000 h (fe0000 h ) fe8000 h fe8000 h 004000 h (004000 h ) 004000 h 004000 h 000900 h (001100 h ) 000d00 h 000d00 h mb90230 series 20 n i/o map (continued) address register register name access resouce name initial value 00 h port 0 data register pdr0 r/w port 0 x x x x x x x x 01 h port 1 data register pdr1 r/w port 1 x x x x x x x x 02 h port 2 data register pdr2 r/w port 2 x x x x x x x x 03 h port 3 data register pdr3 r/w port 3 x x x x x x x x 04 h port 4 data register pdr4 r/w port 4 x x x x x x x x 05 h port 5 data register pdr5 r/w port 5 x x x x x x x x 06 h port 6 data register pdr6 r/w port 6 x x x x x x x x 07 h port 7 data register pdr7 r/w port 7 C x x x x x x x 08 h port 8 data register pdr8 r/w port 8 x x x x x x x x 09 h port 9 data register pdr9 r/w port 9 C x x x x x x x 0a h port a data register pdra r/w port a C C x x x x x x 10 h port 0 direction register ddr0 r/w port 0 0 0 0 0 0 0 0 0 11 h port 1 direction register ddr1 r/w port 1 0 0 0 0 0 0 0 0 12 h port 2 direction register ddr2 r/w port 2 0 0 0 0 0 0 0 0 13 h port 3 direction register ddr3 r/w port 3 0 0 0 0 0 0 0 0 14 h port 4 direction register ddr4 r/w port 4 0 0 0 0 0 0 0 0 15 h port 5 direction register ddr5 r/w port 5 0 0 0 0 0 0 0 0 16 h port 6 direction register ddr6 r/w port 6 0 0 0 0 0 0 0 0 17 h port 7 direction register ddr7 r/w port 7 C 0 0 0 0 0 0 0 18 h port 8 direction register ddr8 r/w port 8 0 0 0 0 0 0 0 0 19 h port 9 direction register ddr9 r/w port 9 C 0 0 0 0 0 0 0 1a h port a direction register ddra r/w port a C C 0 0 0 0 0 0 1b h port 0 resistor register rdr0 r/w port 0 0 0 0 0 0 0 0 0 1c h port 1 resistor register rdr1 r/w port 1 0 0 0 0 0 0 0 0 1d h port 2 resistor register rdr2 r/w port 2 0 0 0 0 0 0 0 0 1e h port 9 pin register odr9 r/w port 9 C 0 0 0 C C C C 1f h port a pin register odra r/w port a C C 0 0 0 0 0 0 20 h mode control register umc r/w uart 0 0 0 0 0 1 0 0 21 h status register usr r/w 0 0 0 1 0 0 0 0 22 h serial input register /serial output register uidr /uodr r/w xxxxxxxx 23 h rate and data register urd r/w 0 0 0 0 C C 0 0 24 h serial mode control status register smcs r/w extended serial i/o interface CCC00000 25 h 00000010 21 mb90230 series (continued) address register register name access resouce name initial value 26 h serial data register sdr r/w extended serial i/o interface xxxxxxxx 27 h reserved area 28 h cycle setting register pcsr w 8-bit ppg timer xxxxxxxx 29 h duty factor setting register pdut w x x x x x x x x 2a h control status register pcntl r/w 00000000 2b h pcnth 0000000C 2c h reserved area 2d h communication prescaler cdcr r/w uart, ckot, i/o, serial if 0CCC1111 2e h clock control register clkr r/w ckot output C C C C C 0 0 0 2f h level comparator lvlc r/w level comparator xxxx0 0 0 0 30 h interrupt/dtp enable register enir r/w dtp/external interrupt CCCC0000 31 h interrupt/dtp factor register eirr r/w C C C C 0 0 0 0 32 h request level setting register elvr r/w 0 0 0 0 0 0 0 0 33 h reserved area 34 h analog input enable register ader r/w 10-bit a/d converter 11111111 35 h reserved area 36 h control status data register adcs0 r/w 0 0 0 0 0 0 0 0 37 h adcs1 00000000 38 h data register adcr0 r xxxxxxxx 39 h adcr1 000000xx 3a h reserved area 3b h reserved area 3c h d/a converter data register 0 dat0 r/w 8-bit d/a converter xxxxxxxx 3d h d/a converter data register 1 dat1 r/w 0 0 0 0 0 0 0 0 3e h d/a control register dacr r/w CCCCCC00 3f h reserved area 40 h pwm data register 0 pwd0 r/w 8-bit pwm0, 1 00000000 41 h pwm data register 1 pwd1 r/w 0 0 0 0 0 0 0 0 42 h control status data register 0, 1 pwc01 r/w 0 0 0 0 0 0 0 0 43 h reserved area 44 h pwm data register 2 pwd2 r/w 8-bit pwm2, 3 00000000 45 h pwm data register 3 pwd3 r/w 0 0 0 0 0 0 0 0 46 h control status register 2, 3 pwc23 r/w 0 0 0 0 0 0 0 0 mb90230 series 22 (continued) address register register name access resouce name initial value 47 h reserved area 48 h pwm data register 4 pwd4 r/w 8-bit pwm4, 5 00000000 49 h pwm data register 5 pwd5 r/w 0 0 0 0 0 0 0 0 4a h control status register 4, 5 pwc45 r/w 0 0 0 0 0 0 0 0 4b h reserved area 4c h data register tcdt r 16-bit free run timer 00000000 4d h 00000000 4e h control status register tccs r/w 0 0 0 0 0 0 0 0 4f h reserved area 50 h compare register 0 ocp0 r/w output compare 0, 1 xxxxxxxx 51 h xxxxxxxx 52 h compare register 1 ocp1 r/w xxxxxxxx 53 h xxxxxxxx 54 h control status register 0, 1 cs00 r/w 0 0 0 0 C C 0 0 55 h cs01 CCC00000 56 h reserved area 57 h reserved area 58 h compare register 2 ocp2 r/w output compare 2, 3 xxxxxxxx 59 h xxxxxxxx 5a h compare register 3 ocp3 r/w xxxxxxxx 5b h xxxxxxxx 5c h control status register 2, 3 cs10 r/w 0 0 0 0 C C 0 0 5d h cs11 CCC00000 5e h reserved area 5f h reserved area 60 h compare register 4 ocp4 r/w output compare 4, 5 xxxxxxxx 61 h xxxxxxxx 62 h compare register 5 ocp5 r/w xxxxxxxx 63 h xxxxxxxx 64 h control status register 4, 5 cs20 r/w 0000CC00 65 h cs21 CCC00000 66 h reserved area 67 h to 6f h reserved area 23 mb90230 series (continued) address register register name access resouce name initial value 70 h capture register 0 icp0 r/w input capture 0, 1 xxxxxxxx 71 h xxxxxxxx 72 h capture register 1 icp1 r/w xxxxxxxx 73 h xxxxxxxx 74 h control status register 0, 1 ics0 r/w 0 0 0 0 0 0 0 0 75 h to 77 h reserved area 78 h capture register 2 icp2 r/w input capture 2, 3 xxxxxxxx 79 h xxxxxxxx 7a h capture register 3 icp3 r/w xxxxxxxx 7b h xxxxxxxx 7c h control status register 2, 3 ics1 r/w 0 0 0 0 0 0 0 0 7d h to 7f h reserved area 80 h op code register eopc r/w serial e 2 prom interface CCCC0000 81 h format status register ects r/w 0 0 0 0 0 0 0 0 82 h data register edat r/w xxxxxxxx 83 h xxxxxxxx 84 h address register eadr r/w 0 0 0 0 0 0 0 0 85 h 00CCC000 86 h to 8f h reserved area 90 h to 9e h system reserved area *1 9f h delayed interrupt source generate/ release register dirr r/w delayed interrupt generation module CCCCCCC0 a0 h standby control register stbyc r/w low-power consumption mode 0001xxxx a1 h reserved area a2 h reserved area a3 h middle address control register macr w external pin *2 a4 h upper address control register hacr w external pin *2 a5 h external pin control register epcr w external pin *2 a6 h reserved area a7 h reserved area a8 h watchdog timer control register twc r/w watchdog timer/ reset xxxxxxxx mb90230 series 24 initial values 0: the initial value for the bit is 0. 1: the initial value for the bit is 1. x: the initial value for the bit is undefined. C: the bit is not used; the initial value is undefined. *1: access inhibited *2: the initial value depends on each bus mode. *3: only this area can be used as the external access area in the area that follows address 0000ff h . access to any address in reserved areas specified in the i/o map table is handled as access to an internal area. an access signal to the external bus is not generated. address register register name access resouce name initial value a9 h timebase timer control register tbtc r/w timebase timer CCC00000 aa h to af h reserved area b0 h interrupt control register 00 icr00 r/w interrupt controller 00000111 b1 h interrupt control register 01 icr01 r/w 0 0 0 0 0 1 1 1 b2 h interrupt control register 02 icr02 r/w 0 0 0 0 0 1 1 1 b3 h interrupt control register 03 icr03 r/w 0 0 0 0 0 1 1 1 b4 h interrupt control register 04 icr04 r/w 0 0 0 0 0 1 1 1 b5 h interrupt control register 05 icr05 r/w 0 0 0 0 0 1 1 1 b6 h interrupt control register 06 icr06 r/w 0 0 0 0 0 1 1 1 b7 h interrupt control register 07 icr07 r/w 0 0 0 0 0 1 1 1 b8 h interrupt control register 08 icr08 r/w 0 0 0 0 0 1 1 1 b9 h interrupt control register 09 icr09 r/w 0 0 0 0 0 1 1 1 ba h interrupt control register 10 icr10 r/w 0 0 0 0 0 1 1 1 bb h interrupt control register 11 icr11 r/w 0 0 0 0 0 1 1 1 bc h interrupt control register 12 icr12 r/w 0 0 0 0 0 1 1 1 bd h interrupt control register 13 icr13 r/w 0 0 0 0 0 1 1 1 be h interrupt control register 14 icr14 r/w 0 0 0 0 0 1 1 1 bf h interrupt control register 15 icr15 r/w 0 0 0 0 0 1 1 1 c0 h to ff h external area *3 25 mb90230 series n interrupt vectors and interrupt control registers for interrupt sources : the request flag is cleared by the ei 2 os interrupt clear signal. : the request flag is cleared by the ei 2 os interrupt clear signal. the stop request is available. : the request flag is not cleared by the ei 2 os interrupt clear signal. interrupt source i 2 os support interrupt vector interrupt control register no. address icr address reset #08 08 h ffffdc h int9 instruction #09 09 h ffffd8 h exceptional #10 0a h ffffd4 h external interrupt (int0) 0 ch #11 0b h ffffd0 h icr00 0000b0 h external interrupt (int1) 1 ch #12 0c h ffffcc h external interrupt (int2) 2 ch #13 0d h ffffc8 h icr01 0000b1 h external interrupt (int3) 3 ch #14 0e h ffffc4 h extended serial i/o interface #15 0f h ffffc0 h icr02 0000b2 h serial e 2 prom interface #17 11 h ffffb8 h icr03 0000b3 h input capture channel 0 #19 13 h ffffb0 h icr04 0000b4 h input capture channel 1 #21 15 h ffffa8 h icr05 0000b5 h input capture channel 2 #23 17 h ffffa0 h icr06 0000b6 h input capture channel 3 #24 18 h ffff9c h output compare channel 0 #25 19 h ffff98 h icr07 0000b7 h output compare channel 1 #26 1a h ffff94 h output compare channel 2 #27 1b h ffff90 h icr08 0000b8 h output compare channel 3 #28 1c h ffff8c h output compare channel 4 #29 1d h ffff88 h icr09 0000b9 h output compare channel 5 #30 1e h ffff84 h 16-bit free run timer overflow #31 1f h ffff80 h icr10 0000ba h timebase timer overflow #32 20 h ffff7c h 8-bit ppg timer #33 21 h ffff78 h icr11 0000bb h level comparator #34 22 h ffff74 h uart reception #35 23 h ffff70 h icr12 0000bc h uart transmission #37 25 h ffff68 h icr13 0000bd h end of a/d conversion #39 27 h ffff60 h icr14 0000be h delayed interrupt #42 2a h ffff54 h icr15 0000bf h stack fault #256 ff h fffc00 h mb90230 series 26 n peripheral resources 1. i/o ports each pin in each port can be specified for input or output by setting the direction register when the corresponding peripheral resource is not set to use that pin. when the data register is read, the value depending on the pin level is read whenever the pin serves for input. when the data register is read with the pin serving for output, the latch value of the data register is read. this also applies to read operation by the read modify write instruction. data register direction register data register read data register write direction register write direction register read pin internal data bus data register direction register read port input/output pull-up resistor (approx. 50 k w ) internal data bus resistor register ? general-purpose i/o port ? port with pull-up resistor setting register 27 mb90230 series data register direction register port input/output pin register internal data bus ? port with open-drain setting register mb90230 series 28 (1) register configuration 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 address: 000000 h address: 000001 h address: 000002 h address: 000003 h address: 000004 h address: 000005 h address: 000006 h address: 000007 h address: 000008 h address: 000009 h address: 00000a h bit p06 p05 p04 p03 p02 p01 p00 p07 p16 p15 p14 p13 p12 p11 p10 p17 p26 p25 p24 p23 p22 p21 p20 p27 p36 p35 p34 p33 p32 p31 p30 p37 p46 p45 p44 p43 p42 p41 p40 p47 p56 p55 p54 p53 p52 p51 p50 p57 p66 p65 p64 p63 p62 p61 p60 p67 p76 p75 p74 p73 p72 p71 p70 p86 p85 p84 p83 p82 p81 p80 p87 p96 p95 p94 p93 p92 p91 p90 pa5 pa4 pa3 pa2 pa1 pa0 port 0 data register (pdr0) port 1 data register (pdr1) port 2 data register (pdr2) port 3 data register (pdr3) port 4 data register (pdr4) port 5 data register (pdr5) port 6 data register (pdr6) port 7 data register (pdr7) port 8 data register (pdr8) port 9 data register (pdr9) port a data register (pdra) 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 address: 000010 h address: 000011 h address: 000012 h address: 000013 h address: 000014 h address: 000015 h address: 000016 h address: 000017 h address: 000018 h address: 000019 h address: 00001a h bit p06 p05 p04 p03 p02 p01 p00 p07 p16 p15 p14 p13 p12 p11 p10 p17 p26 p25 p24 p23 p22 p21 p20 p27 p36 p35 p34 p33 p32 p31 p30 p37 p46 p45 p44 p43 p42 p41 p40 p47 p56 p55 p54 p53 p52 p51 p50 p57 p66 p65 p64 p63 p62 p61 p60 p67 p76 p75 p74 p73 p72 p71 p70 p86 p85 p84 p83 p82 p81 p80 p87 p96 p95 p94 p93 p92 p91 p90 pa5 pa4 pa3 pa2 pa1 pa0 port 0 direction register (ddr0) port 1 direction register (ddr1) port 2 direction register (ddr2) port 3 direction register (ddr3) port 4 direction register (ddr4) port 5 direction register (ddr5) port 6 direction register (ddr6) port 7 direction register (ddr7) port 8 direction register (ddr8) port 9 direction register (ddr9) port a direction register (ddra) 15 14 13 12 11 10 9 8 address: 000034 h bit ade6 ade5 ade4 ade3 ade2 ade1 ade0 ade7 analog input enable register (ader) 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 address: 00001b h address: 00001c h address: 00001d h bit p06 p05 p04 p03 p02 p01 p00 p07 p16 p15 p14 p13 p12 p11 p10 p17 p26 p25 p24 p23 p22 p21 p20 p27 port 0 resistor register (rdr0) port 1 resistor register (rdr1) port 2 resistor register (rdr2) 15/7 14/6 13/5 12/4 11/3 10/2 9/1 8/0 address: 00001e h address: 00001f h bit p96 p95 p94 pa5 pa4 pa3 pa2 pa1 pa0 port 9 pin register (odr9) port a pin register (odra) 29 mb90230 series ports 0 to 5 in the mb90230 series share the external bus and pins. each pin function is selected depending on the bus mode and register settings. *1: the pin can be used as an i/o port by setting the upper and middle address control registers. *2: the pin can be used as an i/o port by setting the external pin control register. pin name function single-chip mode external bus extended mode eprom write 8 bits 16 bits p07 to p00 port d07 to d00 d07 to d00 p17 to p10 port d15 to d08 d15 to d08 p27 to p20 a07 to a00 a07 to a00 p37 to p30 a15 to a08* 1 a15 to a08 p47 to p45 a23 to a16* 1 a23 to a16 p44 p43 to p40 p50 clk* 2 not used p51 rdy* 2 p52 hak * 2 p53 hrq* 2 p54 port wrh * 2 ce p55 wr wrl * 2 oe p56 rd pgm p57 port 0 mb90230 series 30 2. 8-bit pwm (with 6 channels in this series) the pwm module consists of a pair of 8-bit pwm output circuits. the mb90230 series incorporates a set of three pwm modules. they can output a waveform continuously from the port at an arbitrary duty factor according to the register settings. ? 8-bit down counter ? 8-bit data registers ? compare circuit ? control registers (1) register configuration (2) block diagram 000041, 40 h 000045, 44 h 000049, 48 h 15 pwdx pwdx 87 0 pwcxx 70 pwm data registers 0 to 5 control registers 0 to 5 000042 h 000046 h 00004a h bit 8-bit down counter comparator, pwm output section 8-bit data registers control registers bus pwm output 31 mb90230 series 3. uart the uart is a serial i/o port for synchronous or asynchronous communication with external resources. it has the following features: ? full-duplex double buffering ? data transfer synchronous or asynchronous with clock pulses ? multiprocessor mode support (mode 2) ? internal dedicated baud-rate generator ? arbitrary baud-rate setting from external clock input or internal timer ? variable data length (7 to 9 bits (without parity bit); 6 to 8 bits (with parity bit)) ? error detection function (framing, overrun, parity) ? interrupt function (two sources for transmission and reception) ? transfer in nrz format (1) register configuration 8 bits 8 bits usr urd umc uidr (r)/uodr (w) 15 87 0 (r/w) (r/w) pen sbl mc1 mc0 smde rfc scke soe 76 54 3210 rdrf orfe pe tdre rie tie rbf tbf 15 14 13 12 11 10 9 8 d7 d6 d5 d4 d3 d2 d1 d0 76 54 3210 rc2 rc1 rc0 p d8 15 14 13 12 11 10 9 8 md div3 div2 div1 div0 15 14 13 12 11 10 9 8 address: 000020 h address: 000021 h address: 000022 h address: 000023 h address: 00002d h bit bit bit bit bit mode control register (umc) status register (usr) serial input data register serial output data register (uidr/uodr) rate and data register (urd) communication prescaler (cdcr) mb90230 series 32 (2) block diagram control bus dedicated baud-rate clock internal timer external clock clock selector circuit receiving clock transmitting clock reception interrupt (to cpu) sck0 transmission interrupt (to cpu) transmission control circuit transmission start circuit transmission bit counter transmission parity counter sot0 transmission shifter uodr reception control circuit start bit detector received parity counter reception shifter end of reception uidr reception status detection circuit reception error occurrence signal for ei 2 os (to cpu) data bus umc register usr register pen sbl mc1 mc0 smde rfc scke soe rdrf orfe pe tdre rie tie rbf tbf urd register bch rc2 rc1 rc0 p d8 control bus sin0 received bit counter start of transmission 33 mb90230 series 4. extended serial i/o interface this block is a serial i/o interface implemented on a single 8-bit channel that can transfer data in synchronization with clock pulses. it allows the lsb first or msb first option to be selected for data transfer. the serial i/o port to be used can also be selected. there are two serial i/o operation modes available: ? internal shift clock mode: transfers data in synchronization with internal clock pulses. ? external shift clock mode: transfers data in synchronization with clock pulses entered from an external pin (sckx). in this mode, data can be transferred by instructions from the cpu by operating the general-purpose port that shares the external pin (sckx). (1) register configuration (2) block diagram smd2 smd1 smd0 sie sir busy stop strt 15 14 13 12 11 10 9 8 outc mode bds soe scoe 76 54 3210 d7 d6 d5 d4 d3 d2 d1 d0 76 54 3210 address: 000025 h address: 000024 h address: 000026 h bit bit bit serial mode control status register (smcs) serial data register (sdr) internal data bus (msb first) d0 to d7 selecting transfer direction read write sdr (serial data register) internal clock control circuit shift clock counter interrupt request sin1, 2 sot1, 2 sck1, 2 smd2 smd1 smd0 sie sir busy stop strt mode bds d7 to d0 (lsb first) 21 0 soe internal data bus scoe mb90230 series 34 5. a/d converter the a/d converter converts the analog input voltage to a digital value. it has the following features: ? conversion time: 5 m s min. per channel (at 16 mhz machine clock) ? rc-type successive approximation with sample-and-hold circuit ? 8-bit or 10-bit resolution ? eight analog input channels programmable for selection ? a/d conversion mode selectable from the following three: one-shot conversion mode: converts a specified channel once. consecutive conversion mode: converts a specified channel repeatedly. stop conversion mode: converts one channel and suspends its own operation until the next activation (allowing synchronized conversion start). ? conversion mode: single conversion mode: converts one channel (when the start and stop channels are the same). scan conversion mode: converts multiple consecutive channels (when the start and stop channels are different). ? on completion of a/d conversion, the converter can generate an interrupt request for termination of a/d conversion to the cpu. this interrupt generation can activate the ei 2 os to transfer the a/d conversion result to memory, making the converter suitable for continuous operation. ? conversion can be activated by software, external trigger (falling edge), and/or timer (rising edge) as selected. (1) register configuration adcs1 adcs0 15 87 0 control status register bit 000037, 36 h adcr1 adcr0 data register 000039, 38 h ader analog input enable register 000034 h 35 mb90230 series (2) block diagram av cc avrh, avrl an0 an1 an2 an3 an4 an5 an6 an7 mpx input circuit sample-and-hold circuit comparator d/a converter successive approximation register data register decoder a/d control register 0 a/d control register 1 adcr1, 0 adcs1, 0 atg timer interlocked with ppg timer f activation by timer activation trigger operation clock prescaler data bus av ss mb90230 series 36 6. 16-bit i/o timer the 16-bit i/o timer consists of 16-bit free run timer, 6-line output compare, and 4-line input capture modules. the 16-bit i/o timer can output six independent waveforms based on the 16-bit free run timer, allowing the input pulse width and external clock cycle to be measured. (1) outline of functions 16-bit free run timer ( 1) the 16-bit free run timer consists of a 16-bit up-count timer, a control register, and a prescaler. the value output from this timer/counter is used as the base time by the input capture and output compare modules. ? the counter operation clock cycle can be selected from the following four: four internal clock cycles ( f /4, f /16, f /32, f /64) ? the interrupt counter value can be generated by compare/match operation with the overflow register and compare register 0 (compare/match operation requires the mode setting). ? the counter value can be initialized to 0000 h by compare/match operation with the reset register, software clear register, and compare register 0. output compare module ( 6) the output compare module consists of six 16-bit compare registers, compare output latches, and control registers. when the compare value matches the 16-bit free run timer value, this module can generates an interrupt while inverting the output level. ? six compare registers can operate independently, and have each output pin and interrupt flag. ? two compare resisters can be used to control the same output pin. ? the initial value for each output pin can be set. ? the interrupt can be generated by compare/match operation. input capture module ( 4) the input capture module consists of four external input pins and associated capture and control registers. this module can detect an arbitrary edge of the signal input from each external input pin to generate an interrupt while holding the 16-bit free run timer value in the capture register. ? the external input signal edge can be selected from the rising edge, failing edge or both edges. ? four input capture lines can operate independently. ? the interrupts can be generated by a valid edge of external input signals. the extended intelligent i/o service (ei 2 os) can be activated. 37 mb90230 series (2) register configuration tcdt 15 0 timer data register bit 00004c h tccs control status register 00004e h ocp0 to 5 compare register 0 to 5 bit 000050, 52, 58, 5a h 000060, 62 h cs 1 cs 0 control status register 0 to 5 000054, 55 h 00005c, 5d h 000064, 65 h 15 0 ipcp0 to 3 compare register 0 to 3 bit 000070, 72, 78, 7a h ics0 to 3 control status register 0 to 3 000074, 7c h 15 0 ? 16-bit free run timer ? 16-bit output compare module ? 16-bit input capture module mb90230 series 38 (3) block diagram 16-bit free run timer control logic 16-bit timer compare register 0 capture register 0 output compare 0 input capture 0 tq tq tq tq edge selection bus interrupt to each block out 0 out 1 out 2 out 3 in 0 in 1 clear tq tq out 4 out 5 in 2 in 3 10 compare register 1 compare register 2 compare register 3 compare register 4 compare register 5 output compare 1 output compare 2 input capture 1 capture register 1 capture register 2 capture register 3 edge selection edge selection edge selection 39 mb90230 series 7. ppg timer (programmable pulse generator) this module can output the pulse synchronized with an external or software trigger. the cycle and duty factor of the output pulse can be changed arbitrarily by changing the values in two 8-bit registers. pwm function: outputs a pulse in programmable mode while changing the values in the two registers in synchronization with the input trigger. this module can also be used as a d/a converter using an external circuit. single-shot function: detects the trigger input edge to output a single pulse. (1) module configuration this module consists of an 8-bit down counter, prescaler, 8-bit cycle setting register, 8-bit duty factor setting register, 16-bit control register, external trigger input pin, and ppg output pin. (2) register configuration 15 87 0 000028 h pcsr cycle setting register 000029 h pdut duty factor setting register pcnth pcntl control status register 00002b h , 2a h address: bit mb90230 series 40 (3) block diagram prescaler trg input edge detection software trigger enable interrupt selection irq inverted bit ppg output s q r ppg mask cmp p d u t p c s r ck load 8-bit down counter start borrow 1 / f 4 / f 16 / f 64 / f 41 mb90230 series 8. serial e 2 prom interface this module is the interface circuit dedicated to external bit-serial e 2 prom. (1) features ? instruction code support (compatible with the mb8557). ? selectable address length: 8 to 11 bits ? selectable data length: 8 or 16 bits ? automatic address increment function ? transmit/receive data transfer enabled by ei 2 os ? up to 2048-by-16 bit access enabled (at an address length of 11 bits and a data length of 16 bits) (2) register configuration ifen int inte busy adl1 adl0 dtl con 15 14 13 12 11 10 9 8 op3 op2 op1 op0 76 54 3210 d15 d14 d13 d12 d11 d10 d9 d8 15 14 13 12 11 10 9 8 d7 d6 d5 d4 d3 d2 d1 d0 76 54 3210 clk frq a10 a9 a8 15 14 13 12 11 10 9 8 address: 000081 h address: 000080 h address: 000083 h address: 000082 h address: 000085 h bit bit bit bit bit format status register (ects) op code register (eopc) data register (edat) data register (edat) address register (eadr) 15 87 0 status format register data register address register a7 a6 a5 a4 a3 a2 a1 a0 76 54 3210 address: 000084 h bit address register (eadr) bit mb90230 series 42 (3) block diagram op code register address register data register format register bus data register status register prescaler operation clock f machine cycle esk ecs edo edi 43 mb90230 series 9. dtp/external interrupt the data transfer peripheral (dtp) is located between external peripherals and the f 2 mc-16f cpu. it receives a dma request or interrupt request generated by the external peripherals and reports it to the f 2 mc-16f cpu to activate the extended intelligent i/o service or interrupt handler. the user can select two request levels of h and l for extended intelligent i/o service (ei 2 os) or, four request levels of h, l, rising edge, and falling edge for external interrupt requests. (1) register configuration (2) block diagram eirr enir interrupt/dtp enable register 000031 h , 30 h elvr request level setting register 000032 h 15 87 0 bit address: 4 gate 4 source f/f edge detection circuit 3 interrupt dtp source register 4 request level setting register 8 request input f 2 mc-16 bus interrupt dtp source register mb90230 series 44 10. d/a converter this block is an r-2r type d/a converter with 8-bit resolution. the d/a converter incorporates two channels, each of which can be controlled for output independently by the d/a control register. (1) register configuration (2) block diagram da17 da16 da15 da14 da13 da12 da11 da10 15 14 13 12 11 10 9 8 da07 da06 da05 da04 da03 da02 da01 da00 76 54 3210 dae1 dae0 76 54 3210 dat1 address: 00003d h dat0 address: 00003c h dacr address: 00003e h d/a converter data register 1 d/a converter data register 2 d/a control register bit f 2 mc-16 bus da 17 da 16 da 15 da 14 da 13 da 12 da 11 da 10 da 07 da 06 da 05 da 04 da 03 da 02 da 01 da 00 dae1 standby control 2r 2r 2r 2r r r r av cc da17 da16 da15 da11 da10 da output ch. 1 dae0 standby control 2r 2r 2r 2r r r r av cc da07 da06 da05 da01 da00 da output ch. 0 2r 2r 45 mb90230 series 11. level comparator this module compares the input level (by checking whether it is high or low). the module consists of a comparator, 4-bit resistor ladder, and control register. ? the external input can be compared to the internal 4-bit resistor ladder. (1) register configuration (2) block diagram lvlc 8 0 level comparator 00002f h bit address: rd3 rd2 rd1 rd0 cplv int inte cpen resistor ladder bus avrh avrl 4 4-bit d/a s/h cmp comparator analog input interrupt mb90230 series 46 12.watchdog timer and timebase timer the watchdog timer consists of a 2-bit watchdog counter using carry signals from an 18-bit timebase counter as the clock source, a control register, and a watchdog reset control section. the timebase timer consists of an 18-bit timer and an interval interrupt control circuit. (1) register configuration (2) block diagram tbtc wtc 15 87 0 timebase timer control register 0000a9 h , a8 h address: bit tbtc tbc1 tbc0 tbr tbie tbof selector and qr s selector timebase interrupt wtc wt1 wt0 wte ponr stbr wrst erst srst from rst bit in stbyc register rst pin from hardware standby control circuit from power-on occurrence wdgrst to internal reset generator 2-bit counter of clr watchdog reset generator clr 2 12 2 14 2 16 2 18 tbtres clock input timebase timer 2 14 2 16 2 17 2 18 oscillation clock f 2 mc-16 bus 47 mb90230 series 13. delay interruupt generation module the delayed interrupt generation module is used to generate an interrupt for task switching. using this module allows an interrupt request to the f 2 mc-16f cpu to be generated or canceled by software. (1) register configuration (2) block diagram 14. clock output control register the clock output control register outputs the output from the communication prescaler to the pin. (1) register configuration r0 15 14 13 12 11 10 9 8 address: 00009f h dirr read/write ? initial value ? delayed interrupt source generate/release register (? (x) (? (x) (? (x) (? (x) (? (x) (? (x) (? (x) (r/w) (0) bit interrupt source latch delayed interrupt source generate/release decoder f 2 mc-16 bus cken frq1 frq0 15 14 13 12 11 10 9 8 address: 00002e h clkr read/write ? initial value ? clock control register (? (? (? (? (? (? (? (? (? (? (r/w) (0) (r/w) (0) (r/w) (0) bit mb90230 series 48 15.low-power consumption control circuit the low-power consumption control circuit consists of a low-power consumption control register, clock generator, standby status control circuit, and gear divider circuit. these internal circuits implements the sleep, stop, and hardware standby modes as well as the clock gear function. the gear function allows the machine clock cycle to be selected as a division of the frequency of crystal oscillation or external clock input by 1, 2, 4, or 16. (1) register configuration (2) block diagram stbyc 15 87 0 standby control register address: 0000a0 h bit selector 2 14 2 0 selector gear divider circuit 1/1 1/2 1/4 1/16 stbyc clk1 clk0 slp stp osc1 osc0 spl rst internal reset generator wdgrst to watchdog timer internal rst rst pin standby control circuit rst clear hst start pin high-impedance control circuit pin hi-z hst pin interrupt request or rst 2 16 2 17 2 18 clock input time-base timer 2 16 2 17 2 18 resource clock generator cpu clock generator resource clock cpu clock oscillation clock f 2 mc-16 bus 49 mb90230 series n electrical characteristics 1. absolute maximum ratings (v ss = 0.0 v) *1: avrh, avrl, or av cc must not exceed v cc . av ss and avrh must not exceed avrh and av cc , respectively. v cc 3 av cc 3 avrh > avrl 3 av ss 3 v ss *2: v i or v o must not exceed v cc + 0.3 v. warning: permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for externded periods may affect device reliability. 2. recommended operating conditions (v ss = 0.0 v) parameter symbol value unit remarks min. max. power supply voltage v cc v ss C 0.3 v ss + 7.0 v av cc , av ss avrh, avrl v cc C 0.3* 1 v ss + 7.0 v input voltage v i * 2 v ss C 0.3 v cc + 0.3 v output voltage v o * 2 v ss C 0.3 v cc + 0.3 v l level output current i ol ? 20 ma l level average output current i olav 4ma l level total output current s i ol ? 50 ma h level output current i oh ? C10 ma h level average output current i ohav C4ma h level total output current s i oh C50ma power consumption p d 400mw operating temperature t a C40 +70 c storage temperature t stg C55 +150 c parameter symbol value unit remarks min. max. power supply voltage v cc 4.75 5.25 v during normal operation 3.0 5.5 v in stop mode operating temperature t a C40 +70 c mb90230 series 50 3. dc characteristics (v cc = 5.0 v 5%, v ss = 0.0 v, t a = C40 c to +70 c) *1: cmos i/o pin (other than hysteresis pins) *2: hysteresis input pins: p46/trg, p70/atg , p71/esi, p80/int0, p81/int1, p82/out0/int2, p83/out1/int3, p90/in0, p91/in1, p92/in2, p93/in3/ckot, p94/sin0, p96/sck0, pa0/sin1, pa2/sck1, pa3/sin2, pa5/sck2 *3: mode pins md2 to md0 *4: open-drain pins p94 to p96 and pa0 to pa5: set by registers *5: pins with pull-up resistor rst and p00 to p27: set by registers parameter symbol pin name condition value unit remarks min. typ. max. h level input voltage v ih *1 v cc = 5.0 v 5% 0.7 v cc v cc + 0.3 v v ihs *2 0.8 v cc v cc + 0.3 v hysteresis input v ihm *3 v cc C 0.3 v cc + 0.3 v md0 to 2 l level input voltage v il *1 v cc = 5.0 v 5% v ss C 0.3 0.3 v cc v v ils *2 v ss C 0.3 0.2 v cc v hysteresis input v ilm *3 v ss C 0.3 v ss + 0.3 v md0 to 2 h level output voltage v oh *1, *2 v cc = 4.75 v i oh = C2.0 ma 2.4 v l level output voltage v ol *1, *2 v cc = 4.75 v i ol = 1.8 ma 0.4v input leakage current i ih *1, *2, *3 v ss + 4.75 v mb90230 series 52 (2) reset, hardware standby, and trigger input standards (v cc = +5.0 v 5%, v ss = 0.0 v, t a = C40 c to +70 c) *machine cycle: t cyc = 1/machine clock = 1/(f c ? n) f c : oscillation frequency n: gear divide ratio (1, 2, 4, 16) note: clock input is required during reset. the machine cycle at hardware standby input is set to 1/32 divided oscillation. parameter symbol pin name condition value unit remarks min. max. reset input time t rstl rst 5 machine cycle* hardware standby input time t hstl hst 5 machine cycle* a/d start trigger input time t at g x at g 5 machine cycle* ppg start trigger input time t ppgl trg 5 machine cycle* input capture input trigger t inp in0 to in3 5 machine cycle* t rstl , t hstl , t inp t atgx , t ppgt rst hst atg trg in0 to in3 53 mb90230 series (3) power-on reset (v cc = +5.0 v 5%, v ss = 0.0 v, t a = C40 c to +70 c) parameter symbol pin name condition value unit remarks min. max. power supply riseing time t r v cc 50ms power-off time t off 1ms v cc t r 4.5 v 0.2 v t off vcc 5 v 3 v vss ram data refined it is recommended to keep the rising speed of the supply voltage at 50 mv/ms or slower. keep in mind that abrupt changes in supply voltage may cause a power-on reset. mb90230 series 54 (4) uart timing (v cc = +5.0 v 5%, v ss = 0.0 v, t a = C40 c to +70 c) notes: ? these ac characteristics assume the clk synchronous mode. ?c l is the value for load capacity applied to the pin under testing. ?t cyc is the machine cycle (in nanoseconds). parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc internal clock operation output pin: c l = 80 pf 8 t cyc ns sck ? sot delay time t slov C80 80 ns valid sin ? sck - t ivsh 100 ns sck - ? valid sin hold time t shix 60ns serial clock h pulse width t shsl external clock operation output pin: c l = 80 pf 4 t cyc ns serial clock l pulse width t slsh 4 t cyc ns sck ? sot delay time t slov 150ns valid sin ? sck - t ivsh 60ns sck - ? valid sin hold time t shix 60ns sot sck sin t slov t scyc t ivsh t shix sot sck sin t slov t slsh t ivsh t shix t shsl 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v ? internal shift clock mode ? external shift clock mode 55 mb90230 series (5) extended serial i/o timing (v cc = +5.0 v 5%, v ss = 0.0 v, t a = C40 c to +70 c) notes: ? c l is the value for load capacity applied to the pin under testing. ?t cyc is the machine cycle (in nanoseconds). parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc internal clock operation output pin: c l = 80 pf 8 t cyc ns sck ? sot delay time t slov 50ns valid sin ? sck - t ivsh 1 t cyc ns sck - ? valid sin hold time t shix 1 t cyc ns serial clock h pulse width t shsl external clock operation output pin: c l = 80 pf 250 ns external clock: 2 mhz max. serial clock l pulse width t slsh 250ns sck ? sot delay time t slov 2 t cyc ns valid sin ? sck - t ivsh 1 t cyc ns sck - ? valid sin hold time t shix 2 t cyc ns sot sck sin t slov t scyc t ivsh t shix sot sck sin t slov t slsh t ivsh t shix t shsl 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v ? internal shift clock mode ? external shift clock mode mb90230 series 56 5. a/d converter electrical characteristics (av cc = v cc = +5.0 v 5%, av ss = v ss = 0.0 v, +3.0 v avrh C avrl, t a = C40 c to +70 c) * : current applied in cpu stop mode with the a/d converter inactive (v cc = av cc = avrh = 5.5 v). notes: ? the error becomes larger as |avrhCavrl| becomes smaller. ? use the output impedance of the external circuit for analog input under the following conditions: external circuit output impedance < approx. 7 k w ? if the output impedance the external circuit is too high, the analog voltage sampling time may be insufficient. (sampling time = 3.0 m s at a machine clock frequency of 16 mhz) parameter symbol pin name value unit min. typ. max. resolution 1010bit total error 3.0 lsb linearity error 2.0 lsb differential linearity error 1.5 lsb zero transition voltage v ot an0 to an7 C1.5 +0.5 +2.5 lsb full-scale transition voltage v fst avrh C4.5 avrh C1.5 avrh +0.5 lsb conversion time f c = 16 mhz 5.00 m s analog port input current i ain an0 to an7 10 m a analog input voltage avrl avrh v reference voltage avrh avrl av cc v avrl 0 avrh v power supply current i a av cc 5ma i as 5* m a reference voltage supply current i r avrh 200 m a i rs 5* m a variation between channels an0 to an7 4 lsb note: the values shown here are reference values. analog input comparator c 1 c 0 r on2 r on1 r on2 + r on2 = approx. 3 k w c 0 = approx. 60 pf c 1 = approx. 4 pf ? analog input circuit mode 57 mb90230 series 6. a/d glossary ? resolution analog changes that are identifiable with the a/d converter. when the number of bits is 10, analog voltage can be divided into 2 10 = 1024 ? total error difference between actual and logical values. this error is caused by a zero transition error, full-scale transition error, linearity error, differential linearity error, or by noise. ? linearity error the deviation of the straight line connecting the zero transition point (00 0000 0000 ? 00 0000 0001) with the full-scale transition point (11 1111 1111 ? 11 1111 1110) from actual conversion characteristics ? differential linearity error the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value analog input v fst linearity error digital output 11 1111 1111 11 1111 1110 00 0000 0010 00 0000 0001 00 0000 0000 v ot v nt v (n+1)t (1lsb n + v ot ) 1lsb 1022 linearity error - 1 v fst - v ot v nt - (1lsb n + v ot ) v ( n+1)t - v nt 1lsb 1lsb (lsb) (lsb) differential linearity error = = = mb90230 series 58 7. d/a converter electrical characteristics (av cc = v cc = +5.0 v 5%, av ss = v ss = 0.0 v, t a = C40 c to +70 c) *: a load capacity of 20 pf is assumed. parameter symbol pin name value unit min. typ. max. resolution 8 8 bit differential linearity error 0.9 lsb conversion time 10* 20* m s analog output impedance 28 k w 59 mb90230 series 8. serial e 2 prom interface timing (1) e 2 prom interface at an operation clock frequency of 1 mhz (v cc = +5.0 v 5%, v ss = 0.0 v, t a = C40 c to +70 c) (2) e 2 prom interface at an operation clock frequency of 2 mhz (v cc = +5.0 v 5%, v ss = 0.0 v, t a = C40 c to +70 c) parameter symbol value unit remarks min. typ. max. operation cycle t sk 1.0 m s clock h time t skh 0.4 0.5 m s clock l time t skl 0.4 0.5 m s ecs setup time t css 0.3 m s ecs hold time t csh 0.0 m s edo data decision time t pd 0.3 m s edo output hold time t oh 0.5 m s edi setup time t dis 0.0 m s edi hold time t dih 0.4 m s ready - ? ecs t rcsh 0.4 m s ecs l time t csl 0.8 1.0 m s parameter symbol value unit remarks min. typ. max. operation cycle t sk 0.5 m s clock h time t skh 0.2 0.25 m s clock l time t skl 0.2 0.25 m s ecs setup time t css 0.15 m s ecs hold time t csh 0.0 m s edo data decision time t pd 0.15 m s edo output hold time t oh 0.25 m s edi setup time t dis 0.0 m s edi hold time t dih 0.2 m s ready - ? ecs t rcsh 0.2 m s ecs l time t csl 0.4 0.5 m s mb90230 series 60 edo esk ecs t sk t skh determined data determined data t pd t csh edi t dis t css input data input data ecs do (e 2 prom output) busy ready hi-z mb90230 series e 2 prom ecs esk edo edi ecs esk edi edo t dih t st t csl t skl t oh 61 mb90230 series n instructions (412 instructions) table 1 description of instruction table item description mnemonic upper-case letters and symbols: described directry in assembly code lower-case letters: replaced when described in assembly code numbers after lower-case letters: indicates the bit width within the code # indicates the number of bytes ~ indicates the number of cycles see table 4 for details about meanings of letters in items. b indicates the compensation value for calculating the number of actual cycles during execution of instruction. the number of actual cycles during execution of instruction is summed with the value in the cycles column. operation indicates operation of instruction. lh indicates special operations involving the bits 15 through 08 of the accumulator. z: transfers 0 x: extends before transferring : no transfer ah indicates special operations involving the high-order 16 bits in the accumulator. *: transfers from al to ah : no transfer z: transfers 00 h to ah. x: transfers 00 h or ff h to ah by extending al i indicates the status of each of the following flags: i (interrupt enable), s (stack), t (sticky bit), n (negative), z (zero), v (overflow), and c (carry). *: changes due to execution of instruction. : no change. s: set by execution of instruction. r: reset by execution of instruction. s t n z v c rmw indicates whether the instruction is a read-modify-write instruction (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.). *: instruction is a read-modify-write instruction : instruction is not a read-modify-write instruction note: cannot be used for addresses that have different meanings depending on whether they are read or written. mb90230 series 62 table 2 explanation of symbols in table of instructions symbol description a 32-bit accumulator the number of bits used varies according to the instruction. byte: low order 8 bits of al word: 16 bits of al long: 32 bits of al, ah ah high-order 16 bits of a al low-order 16 bits of a sp stack pointer (usp or ssp) pc program counter spcu stack pointer upper limit register spcl stack pointer lower limit register pcb program bank register dtb data bank register adb additional data bank register ssb system stack bank register usb user stack bank register spb current stack bank register (ssb or usb) dpr direct page register brg1 dtb, adb, ssb, usb, dpr, pcb, spb brg2 dtb, adb, ssb, usb, dpr, spb ri r0, r1, r2, r3, r4, r5, r6, r7 rwi rw0, rw1, rw2, rw3, rw4, rw5, rw6, rw7 rwj rw0, rw1, rw2, rw3 rli rl0, rl1, rl2, rl3 dir addr16 addr24 addr24 0 to 15 addr24 16 to 23 compact direct addressing direct addressing physical direct addressing bits 0 to 15 of addr24 bits 16 to 23 of addr24 io i/o area (000000 h to 0000ff h ) #imm4 #imm8 #imm16 #imm32 ext (imm8) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data disp8 disp16 8-bit displacement 16-bit displacement bp bit offset value vct4 vct8 vector number (0 to 15) vector number (0 to 255) ( )b bit address rel ear eam branch specification relative to pc effective addressing (codes 00 to 07) effective addressing (codes 08 to 1f) rlst register list 63 mb90230 series table 3 effective address fields * : the number of bytes for address extension is indicated by the + symbol in the # (number of bytes) column in the table of instructions. code notation address format number of bytes in address extemsion* 00 01 02 03 04 05 06 07 r0 r1 r2 r3 r4 r5 r6 r7 rw0 rw1 rw2 rw3 rw4 rw5 rw6 rw7 rl0 (rl0) rl1 (rl1) rl2 (rl2) rl3 (rl3) register direct ea corresponds to byte, word, and long-word types, starting from the left 08 09 0a 0b @rw0 @rw1 @rw2 @rw3 register indirect 0 0c 0d 0e 0f @rw0 + @rw1 + @rw2 + @rw3 + register indirect with post-increment 0 10 11 12 13 14 15 16 17 @rw0 + disp8 @rw1 + disp8 @rw2 + disp8 @rw3 + disp8 @rw4 + disp8 @rw5 + disp8 @rw6 + disp8 @rw7 + disp8 register indirect with 8-bit displacement 1 18 19 1a 1b @rw0 + disp16 @rw1 + disp16 @rw2 + disp16 @rw3 + disp16 register indirect with 16-bit displacemen 2 1c 1d 1e 1f @rw0 + rw7 @rw1 + rw7 @pc + dip16 addr16 register indirect with index register indirect with index pc indirect with 16-bit displacement direct address 0 0 2 2 mb90230 series 64 table 4 number of execution cycles for each form of addressing * : (a) is used in the cycles (number of cycles) column and column b (correction value) in the table of instructions. table 5 correction values for number of cycles used to calculate number of actual cycles * : (b), (c), and (d) are used in the cycles (number of cycles) column and column b (correction value) in the table of instructions. code operand (a)* number of execution cycles for each from of addressing 00 to 07 ri rwi rli listed in table of instructions 08 to 0b @rwj 1 0c to 0f @rwj + 4 10 to 17 @rwi + disp8 1 18 to 1b @rwj + disp16 1 1c 1d 1e 1f @rw0 + rw7 @rw1 + rw7 @pc + dip16 @addr16 2 2 2 1 operand (b)* (c)* (d)* byte word long internal register + 0 + 0 + 0 internal ram even address + 0 + 0 + 0 internal ram odd address + 0 + 1 + 2 even address not in internal ram + 1 + 1 + 2 odd address not in internal ram + 1 + 3 + 6 external data bus (8 bits) + 1 + 3 + 6 65 mb90230 series table 6 transfer instructions (byte) [50 instructions] for an explanation of (a) and (b), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ b operation lh ah i s t n z v c rmw mov a, dir mov a, addr16 mov a, ri mov a, ear mov a, eam mov a, io mov a, #imm8 mov a, @a mov a, @rli+disp8 mov a, @sp+disp8 movp a, addr24 movp a, @a movn a, #imm4 movx a, dir movx a, addr16 movx a, ri movx a, ear movx a, eam movx a, io movx a, #imm8 movx a, @a movx a,@rwi+disp8 movx a, @rli+disp8 movx a, @sp+disp8 movpx a, addr24 movpx a, @a mov dir, a mov addr16, a mov ri, a mov ear, a mov eam, a mov io, a mov @rli+disp8, a mov @sp+disp8, a movp addr24, a mov ri, ear mov ri, eam movp @a, ri mov ear, ri mov eam, ri mov ri, #imm8 mov io, #imm8 mov dir, #imm8 mov ear, #imm8 mov eam, #imm8 mov @al, ah xch a, ear xch a, eam xch ri, ear xch ri, eam 2 3 1 2 2+ 2 2 2 3 3 5 2 1 2 3 2 2 2+ 2 2 2 2 3 3 5 2 2 3 1 2 2+ 2 3 3 5 2 2+ 2 2 2+ 2 3 3 3 3+ 2 2 2+ 2 2+ 2 2 1 1 2+ (a) 2 2 2 6 3 3 2 1 2 2 1 1 2+ (a) 2 2 2 3 6 3 3 2 2 2 1 2 2+ (a) 2 6 3 3 2 3+ (a) 3 3 3+ (a) 2 3 3 2 2+ (a) 2 3 3+ (a) 4 5+ (a) (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) (b) (b) (b) 0 0 (b) (b) (b) (b) (b) 0 (b) (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2 (b) 0 2 (b) byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? imm8 byte (a) ? ((a)) byte (a) ? ((rli))+disp8) byte (a) ? ((sp)+disp8) byte (a) ? (addr24) byte (a) ? ((a)) byte (a) ? imm4 byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? imm8 byte (a) ? ((a)) byte (a) ? ((rwi))+disp8) byte (a) ? ((rli))+disp8) byte (a) ? ((sp)+disp8) byte (a) ? (addr24) byte (a) ? ((a)) byte (dir) ? (a) byte (addr16) ? (a) byte (ri) ? (a) byte (ear) ? (a) byte (eam) ? (a) byte (io) ? (a) byte ((rli)) +disp8) ? (a) byte ((sp)+disp8) ? (a) byte (addr24) ? (a) byte (ri) ? (ear) byte (ri) ? (eam) byte ((a)) ? (ri) byte (ear) ? (ri) byte (eam) ? (ri) byte (ri) ? imm8 byte (io) ? imm8 byte (dir) ? imm8 byte (ear) ? imm8 byte (eam) ? imm8 byte ((a)) ? (ah) byte (a) ? (ear) byte (a) ? (eam) byte (ri) ? (ear) byte (ri) ? (eam) z z z z z z z z z z z z z x x x x x x x x x x x x x C C C C C C C C C C C C C C C C C C C C z z C C * * * * * * * C * * * C * * * * * * * * C * * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * r * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C * C * C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C * C * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C mb90230 series 66 table 7 transfer instructions (word) [40 instructions] note: for an explanation of (a) and (c), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ b operation lh ah i s t n z v c rmw movw a, dir movw a, addr16 movw a, sp movw a, rwi movw a, ear movw a, eam movw a, io movw a, @a movw a, #imm16 movw a, @rwi+disp8 movw a, @rli+disp8 movw a, @sp+disp8 movpwa, addr24 movpwa, @a movw dir, a movw addr16, a movw sp, # imm16 movw sp, a movw rwi, a movw ear, a movw eam, a movw io, a movw @rwi+disp8, a movw @rli+disp8, a movw @sp+disp8, a movpwaddr24, a movpw@a, rwi movw rwi, ear movw rwi, eam movw ear, rwi movw eam, rwi movw rwi, #imm16 movw io, #imm16 movw ear, #imm16 movw eam, #imm16 movw @al, ah xchw a, ear xchw a, eam xchw rwi, ear xchw rwi, eam 2 3 1 1 2 2+ 2 2 3 2 3 3 5 2 2 3 4 1 1 2 2+ 2 2 3 3 5 2 2 2+ 2 2+ 3 4 4 4+ 2 2 2+ 2 2+ 2 2 2 1 1 2+ (a) 2 2 2 3 6 3 3 2 2 2 2 2 1 2 2+ (a) 2 3 6 3 3 3 2 3+ (a) 3 3+ (a) 2 3 2 2+ (a) 2 3 3+ (a) 4 5+ (a) (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) (c) (c) (c) 0 0 0 0 (c) (c) (c) (c) (c) (c) (c) 0 (c) 0 (c) 0 (c) 0 (c) (c) 0 2 (c) 0 2 (c) word (a) ? (dir) word (a) ? (addr16) word (a) ? (sp) word (a) ? (rwi) word (a) ? (ear) word (a) ? (eam) word (a) ? (io) word (a) ? ((a)) word (a) ? imm16 word (a) ? ((rwi) +disp8) word (a) ? ((rli) +disp8) word (a) ? ((sp) +disp8 word (a) ? (addr24) word (a) ? ((a)) word (dir) ? (a) word (addr16) ? (a) word (sp) ? imm16 word (sp) ? (a) word (rwi) ? (a) word (ear) ? (a) word (eam) ? (a) word (io) ? (a) word ((rwi) +disp8) ? (a) word ((rli) +disp8) ? (a) word ((sp) +disp8) ? (a) word (addr24) ? (a) word ((a)) ? (rwi) word (rwi) ? (ear) word (rwi) ? (eam) word (ear) ? (rwi) word (eam) ? (rwi) word (rwi) ? imm16 word (io) ? imm16 word (ear) ? imm16 word (eam) ? imm16 word ((a)) ? (ah) word (a) ? (ear) word (a) ? (eam) word (rwi) ? (ear) word (rwi) ? (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * C * * * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C * C * C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C * C * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 67 mb90230 series table 8 transfer instructions (long word) [11 instructions] for an explanation of (a) and (d), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ b operation lh ah i s t n z v c rmw movl a, ear movl a, eam movl a, # imm32 movl a, @sp + disp8 movpl a, addr24 movpl a, @a movpl@a, rli movl @sp + disp8, a movpl addr24, a movl ear, a movl eam, a 2 2+ 5 3 5 2 2 3 5 2 2+ 1 3+ (a) 3 4 4 3 5 4 4 2 3+ (a) 0 (d) 0 (d) (d) (d) (d) (d) (d) 0 (d) long (a) ? (ear) long (a) ? (eam) long (a) ? imm32 long (a) ? ((sp) +disp8) long (a) ? (addr24) long (a) ? ((a)) long ((a)) ? (rli) long ((sp) + disp8) ? (a) long (addr24) ? (a) long (ear) ? (a) long (eam) ? (a) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C mb90230 series 68 table 9 addition and subtraction instructions (byte/word/long word) [42 instructions] for an explanation of (a), (b), (c) and (d), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ b operation lh ah i s t n z v c rmw add a, #imm8 add a, dir add a, ear add a, eam add ear, a add eam, a addc a addc a, ear addc a, eam adddc a sub a, #imm8 sub a, dir sub a, ear sub a, eam sub ear, a sub eam, a subc a subc a, ear subc a, eam subdc a 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 2 3 2 3+ (a) 2 3+ (a) 2 2 3+ (a) 3 2 3 2 3+ (a) 2 3+ (a) 2 2 3+ (a) 3 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 0 (b) 0 (b) 0 2 (b) 0 0 (b) 0 byte (a) ? (a) + imm8 byte (a) ? (a) + (dir) byte (a) ? (a) + (ear) byte (a) ? (a) + (eam) byte (ear) ? (ear) + (a) byte (eam) ? (eam) + (a) byte (a) ? (ah) + (al) + (c) byte (a) ? (a) + (ear) + (c) byte (a) ? (a) + (eam) + (c) byte (a) ? (ah) + (al) + (c) (decimal) byte (a) ? (a) C imm8 byte (a) ? (a) C (dir) byte (a) ? (a) C (ear) byte (a) ? (a) C (eam) byte (ear) ? (ear) C (a) byte (eam) ? (eam) C (a) byte (a) ? (ah) C (al) C (c) byte (a) ? (a) C (ear) C (c) byte (a) ? (a) C (eam) C (c) byte (a) ? (ah) C (al) C (c) (decimal) z z z z C z z z z z z z z z C C z z z z C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C C C * * C C C C C C C C * * C C C C addw a addw a, ear addw a, eam addw a, #imm16 addw ear, a addw eam, a addcw a, ear addcw a, eam subw a subw a, ear subw a, eam subw a, #imm16 subw ear, a subw eam, a subcw a, ear subcw a, eam 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 2 3+ (a) 2 2 3+ (a) 2 3+ (a) 2 2 3+ (a) 2 2 3+ (a) 2 3+ (a) 0 0 (c) 0 0 2 (c) 0 (c) 0 0 (c) 0 0 2 (c) 0 (c) word (a) ? (ah) + (al) word (a) ? (a) + (ear) word (a) ? (a) + (eam) word (a) ? (a) + imm16 word (ear) ? (ear) + (a) word (eam) ? (eam) + (a) word (a) ? (a) + (ear) + (c) word (a) ? (a) + (eam) + (c) word (a) ? (ah) C (al) word (a) ? (a) C (ear) word (a) ? (a) C (eam) word (a) ? (a) C imm16 word (ear) ? (ear) C (a) word (eam) ? (eam) C (a) word (a) ? (a) C (ear) C (c) word (a) ? (a) C (eam) C (c) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * C C C C * * C C C C C C * * C C addl a, ear addl a, eam addl a, #imm32 subl a, ear subl a, eam subl a, #imm32 2 2+ 5 2 2+ 5 5 6+ (a) 4 5 6+ (a) 4 0 (d) 0 0 (d) 0 long (a) ? (a) + (ear) long (a) ? (a) + (eam) long (a) ? (a) + imm32 long (a) ? (a) C (ear) long (a) ? (a) C (eam) long (a) ? (a) C imm32 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * C C C C C C 69 mb90230 series table 10 increment and decrement instructions (byte/word/long word) [12 instructions] for an explanation of (a), (b), (c) and (d), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. table 11 compare instructions (byte/word/long word) [11 instructions] for an explanation of (a), (b), (c) and (d), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ b operation lh ah i s t n z v c rmw inc ear inc eam dec ear dec eam 2 2+ 2 2+ 2 3+ (a) 2 3+ (a) 0 2 (b) 0 2 (b) byte (ear) ? (ear) +1 byte (eam) ? (eam) +1 byte (ear) ? (ear) C1 byte (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C * * * * incw ear incw eam decw ear decw eam 2 2+ 2 2+ 2 3+ (a) 2 3+ (a) 0 2 (c) 0 2 (c) word (ear) ? (ear) +1 word (eam) ? (eam) +1 word (ear) ? (ear) C1 word (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C * * * * incl ear incl eam decl ear decl eam 2 2+ 2 2+ 4 5+ (a) 4 5+ (a) 0 2 (d) 0 2 (d) long (ear) ? (ear) +1 long (eam) ? (eam) +1 long (ear) ? (ear) C1 long (eam) ? (eam) C1 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C C * * * * mnemonic # ~ b operation lh ah i s t n z v c rmw cmp a cmp a, ear cmp a, eam cmp a, #imm8 1 2 2+ 2 2 2 2+ (a) 2 0 0 (b) 0 byte (ah) C (al) byte (a) C (ear) byte (a) C (eam) byte (a) C imm8 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * C C C C cmpw a cmpw a, ear cmpw a, eam cmpw a, #imm16 1 2 2+ 3 2 2 2+ (a) 2 0 0 (c) 0 word (ah) C (al) word (a) C (ear) word (a) C (eam) word (a) C imm16 C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * C C C C cmpl a, ear cmpl a, eam cmpl a, #imm32 2 2+ 5 3 4+ (a) 3 0 (d) 0 long (a) C (ear) long (a) C (eam) long (a) C imm32 C C C C C C C C C C C C C C C * * * * * * * * * * * * C C C mb90230 series 70 table 12 unsigned multiplication and division instructions (word/long word) [11 instructions] for an explanation of (b) and (c), refer to table 5, correction values for number of cycle used to calculate number of actual cycles. *1: 3 when dividing into zero, 6 when an overflow occurs, and 14 normally. *2: 3 when dividing into zero, 5 when an overflow occurs, and 13 normally. *3: 5 + (a) when dividing into zero, 7 + (a) when an overflow occurs, and 17 + (a) normally. *4: 3 when dividing into zero, 5 when an overflow occurs, and 21 normally. *5: 4 + (a) when dividing into zero, 7 + (a) when an overflow occurs, and 25 + (a) normally. *6: (b) when dividing into zero or when an overflow occurs, and 2 (b) normally. *7: (c) when dividing into zero or when an overflow occurs, and 2 (c) normally. *8: 3 when byte (ah) is zero, and 7 when byte (ah) is not 0. *9: 3 when byte (ear) is zero, and 7 when byte (ear) is not 0. *10: 4 + (a) when byte (eam) is zero, and 8 + (a) when byte (eam) is not 0. *11: 3 when word (ah) is zero, and 11 when word (ah) is not 0. *12: 3 when word (ear) is zero, and 11 when word (ear) is not 0. *13: 4 + (a) when word (eam) is zero, and 12 + (a) when word (eam) is not 0. mnemonic # ~ b operation lh ah i s t n z v c rmw divu a divu a, ear divu a, eam divuw a, ear divuw a, eam mulu a mulu a, ear mulu a, eam muluw a muluw a, ear muluw a, eam 1 2 2+ 2 2+ 1 2 2+ 1 2 2+ * 1 * 2 * 3 * 4 * 5 * 8 * 9 * 10 * 11 * 12 * 13 0 0 * 6 0 * 7 0 0 (b) 0 0 (c) word (ah) /byte (al) quotient ? byte (al) remainder ? byte (ah) word (a)/byte (ear) quotient ? byte (a) remainder ? byte (ear) word (a)/byte (eam) quotient ? byte (a) remainder ? byte (eam) long (a)/word (ear) quotient ? word (a) remainder ? word (ear) long (a)/word (eam) quotient ? word (a) remainder ? word (eam) byte (ah) byte (al) ? word (a) byte (a) byte (ear) ? word (a) byte (a) byte (eam) ? word (a) word (ah) word (al) ? long (a) word (a) word (ear) ? long (a) word (a) word (eam) ? long (a) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * C C C C C C * * * * * C C C C C C C C C C C C C C C C C 71 mb90230 series table 13 signed multiplication and division instructions (word/long word) [11 insturctions] for an explanation of (b) and (c), refer to table 5, correction values for number of cycles used to calculate number of actual cycles. *1: 3 when dividing into zero, 8 or 18 when an overflow occurs, and 18 normally. *2: 3 when dividing into zero, 10 or 21 when an overflow occurs, and 22 normally. *3: 4 + (a) when dividing into zero, 11 + (a) or 22 + (a) when an overflow occurs, and 23 + (a) normally. *4: when the dividend is positive: 4 when dividing into zero, 10 or 29 when an overflow occurs, and 30 normally. when the dividend is negative: 4 when dividing into zero, 11 or 30 when an overflow occurs, and 31 normally. *5: when the dividend is positive: 4 + (a) when dividing into zero, 11 + (a) or 30 + (a) when an overflow occurs, and 31 + (a) normally. when the dividend is negative: 4 + (a) when dividing into zero, 12 + (a) or 31 + (a) when an overflow occurs, and 32 + (a) normally. *6: (b) when dividing into zero or when an overflow occurs, and 2 (b) normally. *7: (c) when dividing into zero or when an overflow occurs, and 2 (c) normally. *8: 3 when byte (ah) is zero, 12 when the result is positive, and 13 when the result is negative. *9: 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative. *10: 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. *11: 3 when word (ah) is zero, 12 when the result is positive, and 13 when the result is negative. *12: 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative. *13: 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative. note: which of the two values given for the number of execution cycles applies when an overflow error occurs in a div or divw instruction depends on whether the overflow was detected before or after the operation. mnemonic # ~ b operation lh ah i s t n z v c rmw div a div a, ear div a, eam divw a, ear divw a, eam 2 2 2+ 2 2+ * 1 * 2 * 3 * 4 * 5 0 0 * 6 0 * 7 word (ah) /byte (al) quotient ? byte (al) remainder ? byte (ah) word (a)/byte (ear) quotient ? byte (a) remainder ? byte (ear) word (a)/byte (eam) quotient ? byte (a) remainder ? byte (eam) long (a)/word (ear) quotient ? word (a) remainder ? word (ear) long (a)/word (eam) quotient ? word (a) remainder ? word (eam) z z z C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * C C C C C mul a mul a, ear mul a, eam mulw a mulw a, ear mulw a, eam 2 2 2+ 2 2 2+ * 8 * 9 * 10 * 11 * 12 * 13 0 0 (b) 0 0 (b) byte (ah) byte (al) ? word (a) byte (a) byte (ear) ? word (a) byte (a) byte (eam) ? word (a) word (ah) word (al) ? long (a) word (a) word (ear) ? long (a) word (a) word (eam) ? long (a) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C mb90230 series 72 table 14 logical 1 instructions (byte, word) [39 instructions] for an explanation of (a), (b), (c) and (d), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. mnemonic # ~ b operation lh ah i s t n z v c rmw and a, #imm8 and a, ear and a, eam and ear, a and eam, a or a, #imm8 or a, ear or a, eam or ear, a or eam, a xor a, #imm8 xor a, ear xor a, eam xor ear, a xor eam, a not a not ear not eam 2 2 2+ 2 2+ 2 2 2+ 2 2+ 2 2 2+ 2 2+ 1 2 2+ 2 2 3+ (a) 3 3+ (a) 2 2 3+ (a) 3 3+ (a) 2 2 3+ (a) 3 3+ (a) 2 2 3+ (a) 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 (b) 0 2 (b) 0 0 2 (b) byte (a) ? (a) and imm8 byte (a) ? (a) and (ear) byte (a) ? (a) and (eam) byte (ear) ? (ear) and (a) byte (eam) ? (eam) and (a) byte (a) ? (a) or imm8 byte (a) ? (a) or (ear) byte (a) ? (a) or (eam) byte (ear) ? (ear) or (a) byte (eam) ? (eam) or (a) byte (a) ? (a) xor imm8 byte (a) ? (a) xor (ear) byte (a) ? (a) xor (eam) byte (ear) ? (ear) xor (a) byte (eam) ? (eam) xor (a) byte (a) ? not (a) byte (ear) ? not (ear) byte (eam) ? not (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r C C C C C C C C C C C C C C C C C C C C C * * C C C * * C C C * * C * * andw a andw a, #imm16 andw a, ear andw a, eam andw ear, a andw eam, a orw a orw a, #imm16 orw a, ear orw a, eam orw ear, a orw eam, a xorw a xorw a, #imm16 xorw a, ear xorw a, eam xorw ear, a xorw eam, a notw a notw ear notw eam 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 2 2+ 2 2 2 3+ (a) 3 3+ (a) 2 2 2 3+ (a) 3 3+ (a) 2 2 2 3+ (a) 3 3+ (a) 2 2 3+ (a) 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 0 (c) 0 2 (c) 0 0 2 (c) word (a) ? (ah) and (a) word (a) ? (a) and imm16 word (a) ? (a) and (ear) word (a) ? (a) and (eam) word (ear) ? (ear) and (a) word (eam) ? (eam) and (a) word (a) ? (ah) or (a) word (a) ? (a) or imm16 word (a) ? (a) or (ear) word (a) ? (a) or (eam) word (ear) ? (ear) or (a) word (eam) ? (eam) or (a) word (a) ? (ah) xor (a) word (a) ? (a) xor imm16 word (a) ? (a) xor (ear) word (a) ? (a) xor (eam) word (ear) ? (ear) xor (a) word (eam) ? (eam) xor (a) word (a) ? not (a) word (ear) ? not (ear) word (eam) ? not (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r r r r C C C C C C C C C C C C C C C C C C C C C C C C C * * C C C C * * C C C C * * C * * 73 mb90230 series table 15 logical 2 instructions (long word) [6 instructions] for an explanation of (a) and (d), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. table 16 sign inversion instructions (byte/word) [6 instructions] for an explanation of (a), (b) and (c) and refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. table 17 absolute value instructions (byte/word/long word) [3 insturctions] table 18 normalize instructions (long word) [1 instruction] * : 5 when the contents of the accumulator are all zeroes, 5 + (r0) in all other cases. mnemonic # ~ b operation lh ah i s t n z v c rmw andl a, ear andl a, eam orl a, ear orl a, eam xorl a, ear xorl a, eam 2 2+ 2 2+ 2 2+ 5 6+ (a) 5 6+ (a) 5 6+ (a) 0 (d) 0 (d) 0 (d) long (a) ? (a) and (ear) long (a) ? (a) and (eam) long (a) ? (a) or (ear) long (a) ? (a) or (eam) long (a) ? (a) xor (ear) long (a) ? (a) xor (eam) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * * * * r r r r r r C C C C C C C C C C C C mnemonic # ~ b operation lh ah i s t n z v c rmw neg a neg ear neg eam 1 2 2+ 2 2 3+ (a) 0 0 2 (b) byte (a) ? 0 C (a) byte (ear) ? 0 C (ear) byte (eam) ? 0 C (eam) x C C C C C C C C C C C C C C * * * * * * * * * * * * C * * negw a negw ear negw eam 1 2 2+ 2 2 3+ (a) 0 0 2 (c) word (a) ? 0 C (a) word (ear) ? 0 C (ear) word (eam) ? 0 C (eam) C C C C C C C C C C C C C C C * * * * * * * * * * * * C * * mnemonic # ~ b operation lh ah i s t n z v c rmw abs a absw a absl a 2 2 2 2 2 4 0 0 0 byte (a) ? absolute value (a) word (a) ? absolute value (a) long (a) ? absolute value (a) z C C C C C C C C C C C C C C * * * * * * * * * C C C C C C mnemonic # ~ b operation lh ah i s t n z v c rmw nrml a, r0 2 * 0 long (a) ? shifts to the position at which 1 was set first byte (r0) ? current shift count CCCC*CCCC C mb90230 series 74 table 19 shift instructions (byte/word/long word) [27 instructions] for an explanation of (a) and (b), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. *1: 3 when r0 is 0, 3 + (r0) in all other cases. *2: 3 when r0 is 0, 4 + (r0) in all other cases. *3: 3 when imm8 is 0, 3 + (imm8) in all other cases. *4: 3 when imm8 is 0, 4 + (imm8) in all other cases. mnemonic # ~ b operation lh ah i s t n z v c rmw rorc a rolc a rorc ear rorc eam rolc ear rolc eam asr a, r0 lsr a, r0 lsl a, r0 asr a, #imm8 lsr a, #imm8 lsl a, #imm8 2 2 2 2+ 2 2+ 2 2 2 3 3 3 2 2 2 3+ (a) 2 3+ (a) * 1 * 1 * 1 * 3 * 3 * 3 0 0 0 2 (b) 0 2 (b) 0 0 0 0 0 0 byte (a) ? right rotation with carry byte (a) ? left rotation with carry byte (ear) ? right rotation with carry byte (eam) ? right rotation with carry byte (ear) ? left rotation with carry byte (eam) ? left rotation with carry byte (a) ? arithmetic right barrel shift (a, r0) byte (a) ? logical right barrel shift (a, r0) byte (a) ? logical left barrel shift (a, r0) byte (a) ? arithmetic right barrel shift (a, imm8) byte (a) ? logical right barrel shift (a, imm8) byte (a) ? logical left barrel shift (a, imm8) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * C * * C * * * * * * * * * * * * * * * * * * * * * * * * C C C C C C C C C C C C * * * * * * * * * * * * C C * * * * C C C C C C asrw a lsrw a/shrw a lslw a/shlw a asrw a, r0 lsrw a, r0 lslw a, r0 asrw a, #imm8 lsrw a, #imm8 lslw a, #imm8 1 1 1 2 2 2 3 3 3 2 2 2 * 1 * 1 * 1 * 3 * 3 * 3 0 0 0 0 0 0 0 0 0 word (a) ? arithmetic right shift (a, 1 bit) word (a) ? logical right shift (a, 1 bit) word (a) ? logical left shift (a, 1 bit) word (a) ? arithmetic right barrel shift (a, r0) word (a) ? logical right barrel shift (a, r0) word (a) ? logical left barrel shift (a, r0) word (a) ? arithmetic right barrel shift (a, imm8) word (a) ? logical right barrel shift (a, imm8) word (a) ? logical left barrel shift (a, imm8) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * C * * C * * C * r * * * * * * * * * * * * * * * * C C C C C C C C C * * * * * * * * * C C C C C C C C C asrl a, r0 lsrl a, r0 lsll a, r0 asrl a, #imm8 lsrl a, #imm8 lsll a, #imm8 2 2 2 3 3 3 * 2 * 2 * 2 * 4 * 4 * 4 0 0 0 0 0 0 long (a) ? arithmetic right shift (a, r0) long (a) ? logical right barrel shift (a, r0) long (a) ? logical left barrel shift (a, r0) long (a) ? arithmetic right shift (a, imm8) long (a) ? logical right barrel shift (a, imm8) long (a) ? logical left barrel shift (a, imm8) C C C C C C C C C C C C C C C C C C C C C C C C * * C * * C * * * * * * * * * * * * C C C C C C * * * * * * C C C C C C 75 mb90230 series table 20 branch 1 instructions [31 instructions] for an explanation of (a), (c) and (d), refer to table 4, number of execution cycles for each form of addressing, and table 5, correction values for number of cycles used to calculate number of actual cycles. *1: 3 when branching, 2 when not branching. *2: 3 (c) + (b) *3: read (word) branch address. *4: w: save (word) to stack; r: read (word) branch address. *5: save (word) to stack. *6: w: save (long word) to w stack; r: read (long word) branch address. *7: save (long word) to stack. mnemonic # ~ b operation lh ah i s t n z v c rmw bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel bv rel bnv rel bt rel bnt rel blt rel bge rel ble rel bgt rel bls rel bhi rel bra rel jmp @a jmp addr16 jmp @ear jmp @eam jmpp @ear * 3 jmpp @eam * 3 jmpp addr24 call @ear * 4 call @eam * 4 call addr16 * 5 callv #vct4 * 5 callp @ear * 6 callp @eam * 6 callp addr24 * 7 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 2 2+ 3 1 2 2+ 4 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 * 1 2 2 3 4+ (a) 3 4+ (a) 3 4 5+ (a) 5 5 7 8+ (a) 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 (c) 2 (c) (c) 2 (c) 2 (c) * 2 2 (c) branch when (z) = 1 branch when (z) = 0 branch when (c) = 1 branch when (c) = 0 branch when (n) = 1 branch when (n) = 0 branch when (v) = 1 branch when (v) = 0 branch when (t) = 1 branch when (t) = 0 branch when (v) xor (n) = 1 branch when (v) xor (n) = 0 ( (v) xor (n) ) or (z) = 1 ( (v) xor (n) ) or (z) = 0 branch when (c) or (z) = 1 branch when (c) or (z) = 0 branch unconditionally word (pc) ? (a) word (pc) ? addr16 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? (ear), (pcb) ? (ear +2) word (pc) ? (eam), (pcb) ? (eam +2) word (pc) ? ad24 0 to 15 (pcb) ? ad24 16 to 23 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? addr16 vector call linstruction word (pc) ? (ear) 0 to 15, (pcb) ? (ear) 16 to 23 word (pc) ? (eam) 0 to 15, (pcb) ? (eam) 16 to 23 word (pc) ? addr 0 to 15, (pcb) ? addr 16 to 23 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C mb90230 series 76 table 21 branch 2 instructions [20 instructions] for an explanation of (b), (c) and (d), refer to table 5, correction values for number of cycles used to calculate number of actual cycles. *1: 4 when branching, 3 when not branching *2: 5 when branching, 4 when not branching *3: 5 + (a) when branching, 4 + (a) when not branching *4: 6 + (a) when branching, 5 + (a) when not branching *5: 3 (b) + 2 (c) when an interrupt request is generated, 6 (c) when returning from the interrupt. *6: high-speed interrupt return instruction. when an interrupt request is detected during this instruction, the instruction branches to the interrupt vector without performing stack operations when the interrupt is generated. *7: return from stack (word) *8: return from stack (long word) mnemonic # ~ b operation lh ah i s t n z v c rmw cbne a, #imm8, rel cwbne a, #imm16, rel cbne ear, #imm8, rel cbne eam, #imm8, rel cwbne ear, #imm16, rel cwbne eam, #imm16, rel dbnz ear, rel dbnz eam, rel dwbnz ear, rel dwbnz eam, rel int #vct8 int addr16 intp addr24 int9 reti retiq * 6 link #imm8 unlink ret * 7 retp * 8 3 4 4 4+ 5 5+ 3 3+ 3 3+ 2 3 4 1 1 2 2 1 1 1 * 1 * 1 * 1 * 3 * 1 * 3 * 2 * 4 * 2 * 4 14 12 13 14 9 11 6 5 4 5 0 0 0 (b) 0 (c) 0 2 (b) 0 2 (c) 8 (c) 6 (c) 6 (c) 8 (c) 6 (c) * 5 (c) (c) (c) (d) branch when byte (a) 1 imm8 branch when byte (a) 1 imm16 branch when byte (ear) 1 imm8 branch when byte (eam) 1 imm8 branch when word (ear) 1 imm16 branch when word (eam) 1 imm16 branch when byte (ear) = (ear) C 1, and (ear) 1 0 branch when byte (ear) = (eam) C 1, and (eam) 1 0 branch when word (ear) = (ear) C 1, and (ear) 1 0 branch when word (eam) = (eam) C 1, and (eam) 1 0 software interrupt software interrupt software interrupt software interrupt return from interrupt return from interrupt at constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area at constant entry, retrieve old frame pointer from stack. return from subroutine return from subroutine C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r r r r * * C C C C C C C C C C C C C C s s s s * * C C C C C C C C C C C C C C C C C C * * C C C C * * * * * * * * * * C C C C * * C C C C * * * * * * * * * * C C C C * * C C C C * * * * * * * * * * C C C C * * C C C C * * * * * * C C C C C C C C * * C C C C C C C C C C C * C * C C C C C C C C C C 77 mb90230 series table 22 other control instructions (byte/word/long word) [36 instructions] for an explanation of (a) and (c), refer to tables 4 and 5. *1: pcb, adb, ssb, usb, and spb: 1 cycle *4: pop count (c), or push count (c) dtb: 2 cycles *5: 3 when al is 0, 5 when al is not 0. dpr: 3 cycles *6: 4 when al is 0, 6 when al is not 0. *2: 3 + 4 (pop count) *7: 5 when al is 0, 7 when al is not 0. *3: 3 + 4 (push count) mnemonic # ~ b operation lh ah i s t n z v c rmw pushw a pushw ah pushw ps pushw rlst popw a popw ah popw ps popw rlst jctx @a and ccr, #imm8 or ccr, #imm8 mov rp, #imm8 mov ilm, #imm8 movea rwi, ear movea rwi, eam movea a, ear movea a, eam addsp #imm8 addsp #imm16 mov a, brgl mov brg2, a mov brg2, #imm8 nop adb dtb pcb spb ncc cmr movw spcu, #imm16 movw spcl, #imm16 setspc clrspc btscn a btscns a btscnda 1 1 1 2 1 1 1 2 1 2 2 2 2 2 2+ 2 2+ 2 3 2 2 3 1 1 1 1 1 1 1 4 4 2 2 2 2 2 3 3 3 * 3 3 3 3 * 2 9 3 3 2 2 3 2+ (a) 2 1+ (a) 3 3 * 1 1 2 1 1 1 1 1 1 1 2 2 2 2 * 5 * 6 * 7 (c) (c) (c) * 4 (c) (c) (c) * 4 6 (c) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 word (sp) ? (sp) C2, ((sp)) ? (a) word (sp) ? (sp) C2, ((sp)) ? (ah) word (sp) ? (sp) C2, ((sp)) ? (ps) (sp) ? (sp) C2n, ((sp)) ? (rlst) word (a) ? ((sp)), (sp) ? (sp) +2 word (ah) ? ((sp)), (sp) ? (sp) +2 word (ps) ? ((sp)), (sp) ? (sp) +2 (rlst) ? ((sp)) , (sp) ? (sp) context switch instruction byte (ccr) ? (ccr) and imm8 byte (ccr) ? (ccr) or imm8 byte (rp) ? imm8 byte (ilm) ? imm8 word (rwi) ? ear word (rwi) ? eam word(a) ? ear word (a) ? eam word (sp) ? ext (imm8) word (sp) ? imm16 byte (a) ? (brgl) byte (brg2) ? (a) byte (brg2) ? imm8 no operation prefix code for ad space access prefix code for dt space access prefix code for pc space access prefix code for sp space access prefix code for no flag change prefix code for the common register bank word (spcu) ? (imm16) word (spcl) ? (imm16) stack check operation enable stack check operation disable byte (a) ? position of 1 bit in word (a) byte (a) ? position of 1 bit in word (a) 2 byte (a) ? position of 1 bit in word (a) 4 C C C C C C C C C C C C C C C C C C C z C C C C C C C C C C C C C z z z C C C C * C C C C C C C C C C * * C C * C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C * * * C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C * * * C C C C C C C C C C C * * * C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C mb90230 series 78 table 23 bit manipulation instructions [21 instructions] for an explanation of (b), refer to table 5, correction values for number of cycles used to calculate number of actual cycles. *1: 5 when branching, 4 when not branching *2: 7 when condition is satisfied, 6 when not satisfied *3: undefined count *4: until condition is satisfied mnemonic # ~ b operation lh ah i s t n z v c rmw movb a, dir:bp movb a, addr16:bp movb a, io:bp movb dir:bp, a movb addr16:bp, a movb io:bp, a setb dir:bp setb addr16:bp setb io:bp clrb dir:bp clrb addr16:bp clrb io:bp bbc dir:bp, rel bbc addr16:bp, rel bbc io:bp, rel bbs dir:bp, rel bbs addr16:bp, rel bbs io:bp, rel sbbs addr16:bp, rel wbts io:bp wbtc io:bp 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 3 3 3 4 4 4 4 4 4 4 4 4 * 1 * 1 * 1 * 1 * 1 * 1 * 2 * 3 * 3 (b) (b) (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) 2 (b) (b) (b) (b) (b) (b) (b) 2 (b) * 4 * 4 byte (a) ? (dir:bp) b byte (a) ? (addr16:bp) b byte (a) ? (io:bp) b bit (dir:bp) b ? (a) bit (addr16:bp) b ? (a) bit (io:bp) b ? (a) bit (dir:bp) b ? 1 bit (addr16:bp) b ? 1 bit (io:bp) b ? 1 bit (dir:bp) b ? 0 bit (addr16:bp) b ? 0 bit (io:bp) b ? 0 branch when (dir:bp) b = 0 branch when (addr16:bp) b = 0 branch when (io:bp) b = 0 branch when (dir:bp) b = 1 branch when (addr16:bp) b = 1 branch when (io:bp) b = 1 branch when (addr16:bp) b = 1, bit = 1 wait until (io:bp) b = 1 wait until (io:bp) b = 0 z z z C C C C C C C C C C C C C C C C C C * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * C C C C C C C C C C C C C C C * * * * * * C C C C C C * * * * * * * C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * * * * * * * C C C C C C * C C 79 mb90230 series table 24 accumulator manipulation instructions (byte/word) [6 instructions] table 25 string instructions [10 instructions] m: rw0 value (counter value) *1: 3 when rw0 is 0, 2 + 6 (rw0) for count out, and 6n + 4 when match occurs *2: 4 when rw0 is 0, 2 + 6 (rw0) in any other case *3: (b) (rw0) *4: (b) n *5: (b) (rw0) *6: (c) (rw0) *7: (c) n *8: (c) (rw0) mnemonic # ~ b operation lh ah i s t n z v c rmw swap swapw ext extw zext zextw 1 1 1 1 1 1 3 2 1 2 1 2 0 0 0 0 0 0 byte (a) 0 to 7 ? ? (a) 8 to 15 word (ah) ? ? (al) byte code extension word code extension byte zero extension word zero extension C C x C z C C * C x C z C C C C C C C C C C C C C C C C C C C C * * r r C C * * * * C C C C C C C C C C C C C C C C C C mnemonic # ~ b operation lh ah i s t n z v c rmw movs/movsi movsd sceq/sceqi sceqd fils/filsi 2 2 2 2 2 * 2 * 2 * 1 * 1 5m +3 * 3 * 3 * 4 * 4 * 5 byte transfer @ah+ ? @al+, counter = rw0 byte transfer @ahC ? @alC, counter = rw0 byte retrieval @ah+ C al, counter = rw0 byte retrieval @ahC C al, counter = rw0 byte filling @ah+ ? al, counter = rw0 C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * C C * * * C C * * C C C * * C C C C C C movsw/movswi movswd scweq/scweqi scweqd filsw/filswi 2 2 2 2 2 * 2 * 2 * 1 * 1 5m +3 * 6 * 6 * 7 * 7 * 8 word transfer @ah+ ? @al+, counter = rw0 word transfer @ahC ? @alC, counter = rw0 word retrieval @ah+ C al, counter = rw0 word retrieval @ahC C al, counter = rw0 word filling @ah+ ? al, counter = rw0 C C C C C C C C C C C C C C C C C C C C C C C C C C C * * * C C * * * C C * * C C C * * C C C C C C mb90230 series 80 table 26 multiple data transfer instructions [18 instructions] *1: 5 + imm8 5, 256 times when imm8 is zero. *2: 5 + imm8 5 + (a), 256 times when imm8 is zero. *3: number of transfers (b) 2 *4: number of transfers (c) 2 *5:the bank register specified by bnk is the same as for the movs instruction. mnemonic # ~ b operation lh ah i s t n z v c rmw movm @a, @rli, #imm8 movm @a, eam, #imm8 movm addr16, @rli, #imm8 movm addr16, eam, #imm8 movmw @a, @rli, #imm8 movmw @a, eam, #imm8 movmw addr16, @rli, #imm8 movmw addr16, eam, #imm8 movm @rli, @a, #imm8 movm eam, @a, #imm8 movm @rli, addr16, #imm8 movm eam, addr16, #imm8 movmw @rli, @a, #imm8 movmw eam, @a, #imm8 movmw @rli, addr16, #imm8 movmw eam, addr16, #imm8 movm bnk : addr16, * 5 bnk : addr16, #imm8 movmw bnk : addr16, * 5 bnk : addr16, #imm8 3 3+ 5 5+ 3 3+ 5 5+ 3 3+ 5 5+ 3 3+ 5 5+ 7 7 * 1 * 2 * 1 * 2 * 1 * 2 * 1 * 2 * 1 * 2 * 1 * 2 * 1 * 2 * 1 * 2 * 1 * 1 * 3 * 3 * 3 * 3 * 4 * 4 * 4 * 4 * 3 * 3 * 3 * 3 * 4 * 4 * 4 * 4 * 3 * 4 multiple data trasfer byte ((a)) ? ((rli)) multiple data trasfer byte ((a)) ? (eam) multiple data trasfer byte (addr16) ? ((rli)) multiple data trasfer byte (addr16) ? (eam) multiple data trasfer word ((a)) ? ((rli)) multiple data trasfer word ((a)) ? (eam) multiple data trasfer word (addr16) ? ((rli)) multiple data trasfer word (addr16) ? (eam) multiple data trasfer byte ((rli)) ? ((a)) multiple data trasfer byte (eam) ? ((a)) multiple data transfer byte ((rli)) ? (addr16) multiple data transfer byte (eam) ? (addr16) multiple data trasfer word ((rli)) ? ((a)) multiple data trasfer word (eam) ? ((a)) multiple data transfer word ((rli)) ? (addr16) multiple data transfer word (eam) ? (addr16) multiple data transfer byte (bnk:addr16) ? (bnk:addr16) multiple data transfer word (bnk:addr16) ? (bnk:addr16) C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 81 mb90230 series n ordering information model package remarks mb90233pfv-xxx mb90234pfv-xxx 100-pin plastic lqfp (fpt-100p-m05) mb90234pfv 100-pin plastic lqfp (fpt-100p-m05) only es MB90W234zfv 100-pin ceramic sqfp (fpt-100c-c01) only es mb90230 series 82 n package dimensions dimensions in mm (inches) c 1995 fujitsu limited f100007s-2c-3 details of "b" part 16.000.20(.630.008)sq 14.000.10(.551.004)sq 0.50(.0197)typ .007 ?.001 +.003 ?0.03 +0.08 0.18 index 0.10(.004) 0.08(.003) m .059 ?.004 +.008 ?0.10 +0.20 1.50 .005 ?.001 +.002 ?0.02 +0.05 0.127 15.00 12.00 (.472) ref (.591) nom "b" "a" 25 26 1 100 75 51 50 76 0.500.20(.020.008) details of "a" part 0.40(.016)max 0.15(.006)max 0.15(.006) 0.15(.006) 0.100.10 (.004.004) (stand off) 0~10? lead no. (mounting height) c 1995 fujitsu limited f100015sc-1-3 15.000.25 (.5910.10) 16.000.20 (.630.008) 12.00(.472)ref 0.50(.0197)typ 0.200.05 (.008.002) index area 13.60 +0.25 ?0.15 +.010 ?.006 .535 sq 1.70(.067)max 0.90(.035)ref details of "a" part 0(0)min stand off (.020.008) 0.500.20 (.005.002) 0.1250.05 "a" sq sq (mounting height) 100-pin plastic lqfp (fpt-100p-m05) dimensions in mm (inches) 100-pin ceramic lqfp (fpt-100c-c01) 83 mb90230 series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-8588, japan tel: 81(44) 754-3763 fax: 81(44) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, usa tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http://www.fujitsu-ede.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 http://www.fmap.com.sg/ f9901 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. |
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